IDT74SSTUBF32866BBFG8 IDT, Integrated Device Technology Inc, IDT74SSTUBF32866BBFG8 Datasheet - Page 15

• Manufacturer Part Number: IDT74SSTUBF32866BBFG8
• Description: IC BUFFER 25BIT CONF DDR2 96BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTUBF32866BBFG8

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74SSTUBF32866BBFG8

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Timing Requirements Over Recommended Operating Free-Air Temperature
Range
Switching Characteristics Over Recommended Free Air Operating Range
(unless otherwise noted)
Symbol Parameter
t
PDMSS
Symbol
t
t
f
PDM
1
minimum time of t
2
time of t
PDQ
t
t
1
2
f
t
MAX
t
INACT
t
t
PHL
PLH
CLOCK
t
PD
LH
HL
ACT
t
t
SU
t
W
H
1
2
V
V
Design target as per JEDEC specifications.
Production Test. (See Production Test Circuit in TEST CIRCUIT AND WAVEFORM section.)
1
1
REF
REF
2
INACT
Max Input Clock Frequency
Propagation Delay, single bit switching, CLK↑ / CLK↓ to Qn
Propagation Delay, single-bit switching, CLK↑ / CLK↓ to Qn
Propagation Delay, simultaneous switching, CLK↑ / CLK↓ to Qn
Propagation Delay, CLK↑ / CLK↓ to PPO
LOW to HIGH Propagation Delay, CLK↑ / CLK↓ to QERR
HIGH to LOW Propagation Delay, CLK↑ / CLK↓ to QERR
HIGH to LOW Propagation Delay, RESET↓ to PPO to Qn↓
LOW to HIGH Propagation Delay, RESET↓ to QERR↑
, data, and clock inputs must be held at a valid input voltage levels (not floating) for a minimum
must be held at a valid input voltage level and data inputs must be held at valid logic levels for a
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup
(max) after RESET is taken LOW.
Time
Time
Hold
ACT
(max) after RESET is taken HIGH.
DCS before CLK↑ , CLK↓, CSR HIGH; CSR before
CLK↑ , CLK↓, DCS HIGH
DCS before CLK↑ , CLK↓ , CSR LOW
DODT, DOCKE, and data before CLK↑ , CLK↓
PAR_IN before CLK↑ , CLK↓
DCS, DODT, DCKE, and data after CLK↑ , CLK↓
PAR_IN after CLK↑ , CLK↓
15
COMMERCIAL TEMPERATURE GRADE
V
V
Min.
Min.
DD
DD
410
0.6
0.5
0.5
0.5
0.4
0.4
1.1
0.4
0.5
0.9
1
1
= 1.8V ± 0.1V
= 1.8V ± 0.1V
IDT74SSTUBF32866B
Max.
Max.
410
1.5
0.8
1.6
1.7
2.4
15
10
3
3
3
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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