ISL2671286IBZ-T Intersil, ISL2671286IBZ-T Datasheet
ISL2671286IBZ-T
Specifications of ISL2671286IBZ-T
Related parts for ISL2671286IBZ-T
ISL2671286IBZ-T Summary of contents
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... FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Intersil (and design trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 1024 1536 ...
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... GND 4 Ordering Information PART NUMBER (Notes 1, 2) ISL2671286IBZ (Note 3) Coming Soon ISL2671286IPZ NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations) ...
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... Ld SOIC Package (Notes 4, 5 PDIP Package (Notes Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+100°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C = +5V 12.5kHz, f REF ...
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Electrical Specifications +VCC = +5V, V values are +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. A SYMBOL PARAMETER REFERENCE INPUT REF REF Input Range REFLEAK Current Drain DIGITAL INPUT/OUTPUT Logic Family V ...
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Timing Specifications At f CLK operating temperature range, -40°C to +85°C. SYMBOL PARAMETER t Output Data Remains Valid After DCLOCK↓ hDO t DOUT Fall Time f t DOUT Rise Time R t Delay Time, CS/SHDN↓ to DCLOCK↓ CSD t Delay ...
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DCLOCK t EN DOUT VOL = 0.4V VIH = 2.4V CS/SHDN t DIS DOUT 10% FIGURE 5. TIMING PARAMETER DEFINITIONS 6 ISL2671286 VIL = 0.8V DCLOCK t hDO DOUT VOH = VDD - 0.2V VIL = 0.8V DCLOCK t ...
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Typical Performance Characteristics otherwise specified. 2.5 2.0 1.5 1.0 0.5 0 SAMPLE RATE (kHz) FIGURE 6. REFERENCE CURRENT vs SAMPLE RATE 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 REFERENCE ...
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Typical Performance Characteristics otherwise specified. (Continued) 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 8.0 7.5 0.1 1.0 REFERENCE VOLTAGE (V) FIGURE 12. EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE 100 ...
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Typical Performance Characteristics otherwise specified. (Continued) 0 -25 -50 -75 -100 -125 0 2 FREQUENCY (kHz) FIGURE 18. 4096 POINT FFT 0.50 0.25 0.00 -0.25 -0.50 -55 -35 - TEMPERATURE (°C) FIGURE 20. CHANGE IN GAIN vs TEMPERATURE ...
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Typical Performance Characteristics otherwise specified. (Continued) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 SUPPLY VOLTAGE (V) FIGURE 24. DIGITAL INPUT LINE THRESHOLD vs SUPPLY VOLTAGE 10 ISL2671286 At T ...
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Functional Description The ISL2671286 is based on a successive approximation register (SAR) architecture utilizing capacitive charge redistribution digital-to-analog converters (DACs). Figure 26 shows a simplified representation of the converter. During the acquisition phase (ACQ), the differential input is stored on ...
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After reset is complete, a single dummy cycle lasting one conversion must be executed to initialize the switched capacitor track and hold. Once the dummy cycle is complete, the ADC mode is determined by the state of CS/SHDN. At ...
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This facilitates the use of ground planes that can be separated easily. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. ...
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Package Outline Drawing M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 3, 3/11 INDEX AREA TOP VIEW 5.00 (0.197) 4.80 (0.189) 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 15 ISL2671286 DETAIL "A" 6.20 (0.244) 5.80 ...