DS25LV02K Maxim Integrated, DS25LV02K Datasheet - Page 9

• Manufacturer Part Number: DS25LV02K
• Description: EPROM
• Manufacturer: Maxim Integrated

DS25LV02: Low-Voltage 1024-Bit EPROM
CRC GENERATION
The DS25LV02 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address and generates a CRC
during some command protocols. To ensure error-free transmission of the address, the host system can compute a
CRC value from the first 56 bits of the address and compare it to the CRC from the DS25LV02.
The host system is responsible for verifying the CRC value and taking action as a result. The DS25LV02 does not
compare CRC values and does not prevent a command sequence from proceeding as a result of a CRC mismatch.
Proper use of the CRC can result in a communication channel with a very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in
8
5
4
Figure 3, or it can be generated in software using the polynomial X
+ X
+ X
+ 1. Additional information about the
Dallas 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor iButtonÒ Products (www.maxim-ic.com/appnoteindex).
In the circuit in Figure 3, the shift register bits are initialized to 0. Then, starting with the least significant bit of the
family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial
number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value.
Figure 3. 1-Wire CRC Generation Block Diagram
INPUT
MSb
LSb
XOR
XOR
XOR
During some command sequences, the DS25LV02 also generates an 8-bit CRC and provides this value to the bus
master to facilitate validation for the transfer of command, address, and data from the bus master to the
DS25LV02. The DS25LV02 computes an 8-bit CRC for the command and address bytes received from the bus
master for the Read Memory, Read Status and Read/Generate CRC commands to confirm that these bytes have
been received correctly. The CRC generator on the DS25LV02 is also used to provide verification of error-free data
transfer as each EPROM page is sent to the master during a Read Data/Generate CRC command and for the 8
bytes of information in the Status memory field.
In each case where a CRC is used for data transfer validation, the bus master must calculate the CRC value using
the same polynomial function and compare the calculated value to the CRC either stored in the DS25LV02 Net
Address or computed by the DS25LV02. The comparison of CRC values and decision to continue with an
operation are determined entirely by the bus master. There is no circuitry in the DS25LV02 that prevents the
command sequence from proceeding if the stored or calculated CRC from the DS25LV02 and the calculated CRC
from the host do not match.
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the
appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain
or tri-state output drivers. The DS25LV02 uses an open-drain output driver as part of the bidirectional interface
circuitry shown in Figure 4. If a bidirectional pin is not available on the bus master, separate output and input pins
can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. A value between 2kW and 5kW is
recommended. The idle state for the 1-Wire bus is high. If, for any reason, a bus transaction must be suspended,
the bus must be left in the idle state to properly resume the transaction later. Note that if the bus is left low for more
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