MAX11059ECB+T Maxim Integrated, MAX11059ECB+T Datasheet - Page 10

• Manufacturer Part Number: MAX11059ECB+T
• Description: Analog to Digital Converters - ADC 14Bit 8Ch Simult Sampling
• Manufacturer: Maxim Integrated

Specifications of MAX11059ECB+T

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 85.3 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3478 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 8
• Voltage Reference: 4.096 V

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
10
MAX11047
(TQFN-EP)
22, 28, 35,
23, 27, 33,
38, 44, 48
7, 21, 50
8, 20, 51
24, 30,
25, 31,
26, 29,
43, 49
41, 47
40, 46
42, 45
______________________________________________________________________________________
10
11
12
13
14
15
16
17
18
19
32
34
36
1
2
3
4
5
6
9
MAX11048
(TQFN-EP)
22, 28, 35,
23, 27, 33,
38, 44, 48
7, 21, 50
8, 20, 51
24, 30,
25, 31,
43, 49
41, 47
40, 46
26, 45
PIN
10
11
12
13
14
15
16
17
18
19
29
32
36
1
2
3
4
5
6
9
(TQFN-EP)
MAX11049
22, 28, 35,
23, 27, 33,
38, 44, 48
7, 21, 50
8, 20, 51
24, 30,
25, 31,
43, 49
41, 47
40, 46
10
11
12
13
14
15
16
17
18
19
26
29
36
—
1
2
3
4
5
6
9
DB3/CR3
DB2/CR2
DB1/CR1
DB0/CR0
CONVST
AGNDS
NAME
DGND
AGND
REFIO
DVDD
SHDN
AVDD
DB13
DB12
DB11
DB10
EOC
RDC
CH0
CH1
DB9
DB8
DB7
DB6
DB5
DB4
I.C.
16-Bit Parallel Data Bus Digital Output Bit 13
16-Bit Parallel Data Bus Digital Output Bit 12
16-Bit Parallel Data Bus Digital Output Bit 11
16-Bit Parallel Data Bus Digital Output Bit 10
16-Bit Parallel Data Bus Digital Output Bit 9
16-Bit Parallel Data Bus Digital Output Bit 8
Digital Ground
Digital Supply. Bypass to DGND with a 0.1µF capacitor at each DV
16-Bit Parallel Data Bus Digital Output Bit 7
16-Bit Parallel Data Bus Digital Output Bit 6
16-Bit Parallel Data Bus Digital Output Bit 5
16-Bit Parallel Data Bus Digital Output Bit 4
16-Bit Parallel Data Bus Digital Output Bit 3/Configuration Register Input Bit 3
16-Bit Parallel Data Bus Digital Output Bit 2/Configuration Register Input Bit 2
16-Bit Parallel Data Bus Digital Output Bit 1/Configuration Register Input Bit 1
16-Bit Parallel Data Bus Digital Output Bit 0/Configuration Register Input Bit 0
Active-Low End of Conversion Output. EOC goes low when conversion is
completed. EOC goes high when a conversion is initiated.
Convert Start Input. Rising edge of CONVST ends sample and starts a
conversion on the captured sample. The ADC is in acquisition mode when
CONVST is low and CONVST mode = 0.
Shutdown Input. If SHDN is held high, the entire device enters and stays in a
low-current state. Contents of the Configuration register are not lost when in
the shutdown state.
Reference Buffer Decoupling. Connect all RDC outputs together. Bypass to
AGND with at least an 80µF total capacitance. See the Layout, Grounding,
and Bypassing section.
Signal Ground. Connect all AGND and AGNDS inputs together on PWB.
Analog Supply Input. Bypass AV
AV
Analog Ground. Connect all AGND inputs together.
Internally Connected. Connect to AGND
Channel 0 Analog Input
Channel 1 Analog Input
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
DD
input.
DD
FUNCTION
to AGND with a 0.1µF capacitor at each
Pin Description
DD
input.