MAX11059ECB+T Maxim Integrated, MAX11059ECB+T Datasheet - Page 14

• Manufacturer Part Number: MAX11059ECB+T
• Description: Analog to Digital Converters - ADC 14Bit 8Ch Simult Sampling
• Manufacturer: Maxim Integrated

Specifications of MAX11059ECB+T

• Rohs: yes
• Number Of Channels: 8
• Architecture: SAR
• Conversion Rate: 250 KSPs
• Resolution: 14 bit
• Input Type: Single-Ended
• Snr: 85.3 dB
• Interface Type: Parallel
• Operating Supply Voltage: 2.7 V to 5.25 V, 4.75 V to 5.25 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 3478 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 8
• Voltage Reference: 4.096 V

4-/6-/8-Channel, 16-/14-Bit,
Simultaneous-Sampling ADCs
The MAX11047/MAX11048/MAX11049 and MAX11057/
MAX11058/MAX11059 are fast, low-power ADCs that
combine 4, 6, or 8 independent ADC channels in a sin-
gle IC. Each channel includes simultaneously sampling
independent T/H circuitry that preserves relative phase
information between inputs making the devices ideal for
motor control and power monitoring. The devices are
available with a 0 to 5V input range that features
±20mA overrange, fault-tolerant inputs. The devices
operate with a single 4.75V to 5.25V supply. A separate
2.7V to 5.25V supply for digital circuitry makes the
devices compatible with low-voltage processors.
The devices perform conversions for all channels in paral-
lel by activating independent ADCs. Results are available
through a high-speed, 20MHz, parallel data bus after a
conversion time of 3µs following the end of a sample. The
14
MAX11057
(TQFP-EP)
______________________________________________________________________________________
41
42
44
61
62
63
64
—
—
—
—
—
MAX11058
(TQFP-EP)
PIN
41
39
42
44
47
61
62
63
64
—
—
—
Detailed Description
MAX11059
(TQFP-EP)
41
37
39
42
44
47
50
61
62
63
64
—
NAME
REFIO
DB13
CH2
CH3
CH4
CH5
CH6
CH7
WR
RD
CS
EP
External Reference Input/Internal Reference Output. Place a 0.1µF capacitor
from REFIO to AGND.
Channel 2 Analog Input
Channel 3 Analog Input
Channel 4 Analog Input
Channel 5 Analog Input
Channel 6 Analog Input
Channel 7 Analog Input
Active-Low Write Input. Drive WR low to write to the ADC. Configuration
registers are loaded on the rising edge of WR.
Active-Low Chip-Select Input. Drive CS low when reading from or writing to
the ADC.
Active-Low Read Input. Drive RD low to read from the ADC. Each rising edge
of RD advances the channel output on the data bus.
14-Bit Parallel Data Bus Digital Out Bit 13
Exposed Pad. Internally connected to AGND. Connect to a large ground
plane to maximize thermal performance. Not intended as an electrical
connection point.
data bus is bidirectional and allows for easy program-
ming of the configuration register. The devices feature a
reference buffer, which is driven by an internal bandgap
reference circuit (V
external reference or bypass with a 0.1µF capacitor to
ground when using the internal reference.
To preserve phase information across all channels,
each input includes a dedicated T/H circuitry. The input
tracking circuitry provides a 4MHz small-signal band-
width, enabling the device to digitize high-speed tran-
sient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Use anti-alias filtering
to avoid high-frequency signals being aliased into the
frequency band of interest.
Pin Description (continued)
FUNCTION
REFIO
= 4.096V). Drive REFIO with an
Track and Hold (T/H)
Analog Inputs