DS2164Q+T&R Maxim Integrated, DS2164Q+T&R Datasheet - Page 7

• Manufacturer Part Number: DS2164Q+T&R
• Description: Digital Signal Processors & Controllers - DSP, DSC
• Manufacturer: Maxim Integrated
• Series: DS2164r

Specifications of DS2164Q+T&R

• Maximum Operating Temperature: + 70 C
• Package / Case: PLCC-28
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Part # Aliases: 90-2164Q+TRL

DS2164Q
TIME SLOT ASSIGNMENT/ORGANIZATION
On-board counters establish when PCM and ADPCM I/O occur. The counters are programmed by the
time slot registers. Time slot size (number of bits wide) is determined by the state of CP/
. The number
EX
of time slots available is determined by the state of both CP/
and U/
(Figures 7 through 10). For
EX
A
= 1) and it is set to expect m-law data
example, if the X channel is set to compress (CP/
EX
(U/
= 1), then the input port (XIN) is set up for 32 8-bit time slots and the output port (XOUT) is set up
A
for 64 4-bit time slots. The time slot organization is not dependent on which algorithm has been selected.
Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX
or CLKY after the frame sync.
Figure 7. m-LAW PCM INTERFACE
Figure 8. m-LAW ADPCM INTERFACE
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