MC14490PG ON Semiconductor, MC14490PG Datasheet - Page 7

IC ELIMINATOR BOUNCE HEX 16DIP

MC14490PG

Manufacturer Part Number
MC14490PG
Description
IC ELIMINATOR BOUNCE HEX 16DIP
Manufacturer
ON Semiconductor
Series
4000r
Datasheets

Specifications of MC14490PG

Logic Type
Contact Bounce Eliminator
Supply Voltage
3 V ~ 18 V
Number Of Bits
6
Operating Temperature
-55°C ~ 125°C
Mounting Type
Through Hole
Package / Case
16-DIP (0.300", 7.62mm)
Supply Voltage (max)
18 V
Supply Voltage (min)
3 V
Mounting Style
Through Hole
Number Of Circuits
Hex
Current, Supply
550 μA
Function Type
6-Channels
Logic Function
Bounce Eliminator
Package Type
PDIP-16
Temperature, Operating, Range
-55 to +125 °C
Voltage, Supply
3 to 18 VDC
Logic Case Style
DIP
No. Of Pins
16
Supply Voltage Range
3V To 18V
Operating Temperature Range
-55°C To +125°C
Filter Terminals
DIP
Rohs Compliant
Yes
Clock Frequency Max
4.5MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MC14490PGOS

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ASYMMETRICAL TIMING
delays are required (such as a fast attack/slow release timer.)
Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be
interchanged. The clock out lead can then be used to feed
clock signals to the other MC14490 packages where the
asymmetrical input/output timing is required.
LATCHED OUTPUT
using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes
low. This will hold the output low even though the input has
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier.
In applications where different leading and trailing edge
The contents of the Bounce Eliminator can be latched by
CLOCK
Figure 6. Fast Attack/Slow Release Circuit
EXTERNAL
CLOCK
Figure 7. Latched Output Circuit
A
OSC
OSC
IN
f
C
in
in
IN
UNLATCH = 0
MC14011B
MC14490
÷ N
LATCH = 1
MC14011B
MC14490
OUT
B
f
C/N
OUT
TYPICAL APPLICATIONS
OSC
OSC
out
out
http://onsemi.com
7
MULTIPLE TIMING SIGNALS
be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
it is required to have a single pulse output for a single
operation (make) of the push button or relay contact. This
only requires the series connection of two Bounce
Eliminator circuits, one inverter, and one NOR gate in order
to generate the signal AB as shown in Figures 9 and 10. The
signal AB is four clock periods in length. If the inverter is
switched to the A output, the pulse AB will be generated
upon release or break of the contact. With the use of a few
additional parts many different pulses and waveshapes may
be generated.
As shown in Figure 8, the Bounce Eliminator circuits can
One application of the above is shown in Figure 9, where
Figure 8. Multiple Timing Circuit Connections
OSC
in
A
B
C
D
E
14
12
10
F
1
3
5
7
in
in
in
in
in
in
CLOCK
B.E. 1
B.E. 2
B.E. 3
B.E. 4
B.E. 5
B.E. 6
15
13
11
2
4
6
9
OSC
out
A
B
C
D
E
F
out
out
out
out
out
out

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