74AUP1T58GM,132 NXP Semiconductors, 74AUP1T58GM,132 Datasheet - Page 17

• Manufacturer Part Number: 74AUP1T58GM,132
• Description: IC LP CONFIG GATE V-XLATR 6XSON
• Manufacturer: NXP Semiconductors
• Series: 74AUPr

Specifications of 74AUP1T58GM,132

• Logic Function: Translator
• Number Of Bits: 3
• Input Type: Voltage
• Output Type: Voltage
• Number Of Channels: 3
• Number Of Outputs/channel: 1
• Differential - Input:output: No/No
• Propagation Delay (max): 3.8ns
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 6-XSON (Micropak™), SOT-886
• Supply Voltage: 2.3 V ~ 3.6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Other names: 568-4749-2; 74AUP1T58GM,132; 74AUP1T58GM-H; 74AUP1T58GM-H; 935280467132

NXP Semiconductors
18. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
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18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic configurations . . . . . . . . . . . . . . . . . . . . . 4
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Low-power configurable gate with voltage-level translator
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
74AUP1T58
Document identifier: 74AUP1T58_1
Date of release: 6 March 2008
All rights reserved.