NVT2002DP,118 NXP Semiconductors, NVT2002DP,118 Datasheet
NVT2002DP,118
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NVT2002DP,118 Summary of contents
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NVT2001; NVT2002 Bidirectional voltage level translator for open-drain and push-pull applications Rev. 1 — 30 August 2010 1. General description The NVT2001/02 are bidirectional voltage level translators operational from 1 3 and 1 ...
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... NXP Semiconductors Low 3.5 Ω ON-state connection between input and output ports provides less signal distortion 5 V tolerant I/O ports to support mixed-mode signal operation High-impedance An and Bn pins for EN = LOW Lock-up free operation Flow through pinout for ease of printed-circuit board trace routing ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning 5.1.1 1-bit in XSON6 package Fig 2. 5.1.2 2-bit in TSSOP8, XSON8U, HXSON8U, XSON8 and XQFN8U packages VREFA Fig 3. terminal 1 index area Fig 5. NVT2001_NVT2002 Product data sheet GND VREFA A1 Transparent top view Pin configuration for XSON6 1 8 GND ...
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... NXP Semiconductors Fig 7. 5.2 Pin description Table 2. Symbol GND VREFA VREFB EN [1] 1-bit NVT2001 available in XSON6 package. [2] 2-bit NVT2002 available in TSSOP8, VSSOP8, XSON8, HXSON8, XQFN8U packages. NVT2001_NVT2002 Product data sheet terminal 1 index area GND 1 VREFA Transparent top view Pin configuration for XQFN8U ...
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... NXP Semiconductors 6. Functional description Refer to 6.1 Function table Table HIGH level LOW level. Input [ controlled by the V operation. 7. Application design-in information The NVT2001/02 can be used in level translation applications for interfacing devices or systems operating at different interface voltages with one another. The NVT2001/02 is ideal for use in applications where an open-drain driver is connected to the data I/Os. The NVT2001/02 can also be used in applications where a push-pull driver is connected to the data I/Os ...
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... NXP Semiconductors Table 4. Refer to Symbol V ref(B) V I(EN) V ref(A) I sw(pass) I ref T amb [1] All typical values are at T (1) In the Enabled mode, the applied enable voltage V (2) Note that the enable time and the disable time are essentially controlled by the RC time constant of Fig 9. ...
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... NXP Semiconductors 1.8 V 1.5 V 1.2 V 1.0 V Fig 10. Bidirectional translation to multiple higher voltage levels 7.2 Bidirectional translation For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled to HIGH side V regulate the EN input. A filter capacitor on VREFB is recommended. The master output ...
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... NXP Semiconductors 7.3 Sizing pull-up resistor The pull-up resistor value needs to limit the current through the pass transistor when the ON state to about 15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher than 15 mA, the pass voltage also is higher in the ON state ...
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... NXP Semiconductors chip/terminating end of the wire when the transition time is shorter than the time of flight of the wire because the NVT20xx looks like a high-impedance compared to the wire. If the wire is not too long and the lumped capacitance is not excessive the signal will only be slightly degraded by the series resistance added by passing through the NVT20xx ...
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... NXP Semiconductors 9. Recommended operating conditions Table 7. Symbol V I/O [1] V ref(A) [1] V ref(B) V I(EN) I sw(pass) T amb [1] V ref(A) 10. Static characteristics Table 8. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter V input clamping voltage IK I HIGH-level input current IH C input capacitance on pin EN ...
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... NXP Semiconductors 10 R on(typ) (Ω 1.5 V I(EN) 8 2.3 V 3 −40 − mA on(typ) (Ω −40 − Fig 11. Typical ON-state resistance versus ambient temperature NVT2001_NVT2002 Product data sheet 002aaf313 R on(typ) (Ω 100 T (°C) amb 002aaf315 R on(typ) (Ω 100 T (°C) amb = 3.0 V I(EN) All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Open-drain drivers Table 9. − amb specified. Symbol Refer to t PLH t PHL [1] See graphs based on R 5.5 V 200 kΩ 0.1 μF 1.5 V swing SIGNAL GENERATOR Fig 12. AC test setup from output under test a. Load circuit S2 = translating down, and same voltage. ...
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... NXP Semiconductors 12. Performance curves t up-translation is typically dominated by the RC time constant, i.e., PLH × L(tot typically dominated by the external pull-down driver + R PHL compared to the t Enable/disable times are dominated by the RC time constant on the EN pin since the transistor turn off is on the order of ns, but the enable the order of ms. ...
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... NXP Semiconductors 13. Package outline XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 18. Package outline SOT996-2 (XSON8U) ...
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... NXP Semiconductors HXSON8U: plastic thermal enhanced extremely thin small outline package; no leads; 8 terminals; UTLP based; body 1.35 x 1 terminal 1 index area terminal 1 e index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.75 mm 0.5 0.00 0.15 1.65 OUTLINE ...
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... NXP Semiconductors XSON8: extremely thin small outline package; no leads; 8 terminals; body 1. 0.5 mm terminal 1 index area (2) (4× terminal 1 index area Dimensions (1) Unit max 0.5 0.04 0.20 1.40 mm nom 0.15 1.35 min 0.12 1.30 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 22. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Soldering: reflow soldering footprint for SOT1089 Footprint information for reflow soldering of XSON8 package Dimensions in mm solder paste = solder land ...
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... NXP Semiconductors 16. Abbreviations Table 12. Acronym CDM ESD GTL HBM 2 I C-bus I/O LVTTL MM PRR RC 17. Revision history Table 13. Revision history Document ID Release date NVT2001_NVT2002 v.1 20100830 NVT2001_NVT2002 Product data sheet Abbreviations Description Charged Device Model ElectroStatic Discharge Gunning Transceiver Logic Human Body Model ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... Product data sheet NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.1.1 1-bit in XSON6 package . . . . . . . . . . . . . . . . . . 3 5.1.2 2-bit in TSSOP8, XSON8U, HXSON8U, XSON8 and XQFN8U packages 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Application design-in information ...