C8051F960-A-GQ Silicon Labs, C8051F960-A-GQ Datasheet - Page 296

• Manufacturer Part Number: C8051F960-A-GQ
• Description: 8-bit Microcontrollers - MCU 128KB DC-DC LCD AES
• Manufacturer: Silicon Labs

Specifications of C8051F960-A-GQ

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 24.5 MHz
• Program Memory Size: 128 KB
• Data Ram Size: 8 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.8 V to 3.8 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: QFP-80
• Mounting Style: SMD/SMT

C8051F96x
24.1. SmaRTClock Interface
The SmaRTClock Interface consists of three registers: RTC0KEY, RTC0ADR, and RTC0DAT. These inter-
face registers are located on the CIP-51’s SFR map and provide access to the SmaRTClock internal regis-
ters listed in Table 24.1. The SmaRTClock internal registers can only be accessed indirectly through the
SmaRTClock Interface.
296
SmaRTClock
0x08–0x0B
0x0C–0x0F
0x00–0x03
0x10–0x13
Address
0x04
0x05
0x06
0x07
SmaRTClock
CAPTUREn SmaRTClock Capture
ALARM0Bn
ALARM1Bn
ALARM2Bn
RTC0XCN
RTC0XCF
Register
RTC0CN
RTC0CF
Table 24.1. SmaRTClock Internal Registers
Registers
SmaRTClock Control
Register
SmaRTClock Oscillator
Control Register
SmaRTClock Oscillator
Configuration Register
SmaRTClock
Configuration Register
SmaRTClock Alarm
Registers
SmaRTClock Alarm
Registers
SmaRTClock Alarm
Registers
Register Name
Rev. 0.5
Four Registers used for setting the 32-bit
SmaRTClock timer or reading its current value.
Controls the operation of the SmaRTClock State
Machine.
Controls the operation of the SmaRTClock
Oscillator.
Controls the value of the progammable
oscillator load capacitance and
enables/disables AutoStep.
Contains an alarm enable and flag for each
SmaRTClock alarm.
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
Four registers used for setting or reading the
32-bit SmaRTClock alarm value.
Description