SST39VF320-70-4C-B3KE Microchip Technology, SST39VF320-70-4C-B3KE Datasheet - Page 2

• Manufacturer Part Number: SST39VF320-70-4C-B3KE
• Description: Flash 2M X 16 70ns
• Manufacturer: Microchip Technology

Specifications of SST39VF320-70-4C-B3KE

• Product Category: Flash
• Rohs: yes
• Memory Size: 32 Mbit
• Interface Type: Parallel
• Access Time: 70 ns
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TFBGA-48
• Organization: 2 MB x 16

Preliminary Specifications
The SST39VF320 also have the Auto Low Power mode
which puts the device in a near standby mode after data
has been accessed with a valid Read operation. This
reduces the I
typically 3 µA. The Auto Low Power mode reduces the typi-
cal I
read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition
used to initiate another Read cycle, with no access time
penalty. Note that the device does not enter Auto Low
Power mode after power-up with CE# held steadily low until
the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF320 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
Word-Program Operation
The SST39VF320 are programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Pro-
gram operation, once initiated, will be completed within 10
µs. See Figures 4 and 5 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 16 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during the internal Program opera-
tion are ignored.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-by-
block) basis. The SST39VF320 offer both Sector-Erase
and Block-Erase modes. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
©2003 Silicon Storage Technology, Inc.
DD
active read current to the range of 2 mA/MHz of
DD
active read current from typically 9 mA to
2
is based on uniform block size of 32 KWord. The Sector-
Erase operation is initiated by executing a six-byte com-
mand sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for tim-
ing waveforms. Any commands issued during the Sector-
or Block-Erase operation are ignored.
Chip-Erase Operation
The SST39VF320 provide a Chip-Erase operation, which
allows the user to erase the entire memory array to the “1”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued dur-
ing the Chip-Erase operation are ignored.
Write Operation Status Detection
The SST39VF320 provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ
Toggle Bit (DQ
enabled after the rising edge of WE#, which initiates the
internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to con-
flict with either DQ
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejec-
tion is valid.
32 Mbit Multi-Purpose Flash
6
). The End-of-Write detection mode is
7
or DQ
6
. In order to prevent spurious
SST39VF320
S71143-02-000
7
) and
11/03