PCAL6416APW,118 NXP Semiconductors, PCAL6416APW,118 Datasheet - Page 12

• Manufacturer Part Number: PCAL6416APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
PCAL6416A
Product data sheet
7.4.3 Polarity inversion register pair (04h, 05h)
7.4.4 Configuration register pair (06h, 07h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write operation is described in
Section
Table 11.
Table 12.
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write operation is described in
register pair read operation is described in
Table 13.
Table 14.
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
Bit
Symbol
Default
8.2.
Polarity inversion port 0 register (address 04h)
Polarity inversion port 1 register (address 05h)
Configuration port 0 register (address 06h)
Configuration port 1 register (address 07h)
N0.7
N1.7
C0.7
C1.7
7
0
7
0
7
1
7
1
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 24 December 2012
N0.6
N1.6
C0.6
C1.6
6
0
6
0
6
1
6
1
Low-voltage translating 16-bit I
Section
N0.5
N1.5
C0.5
C1.5
5
0
5
0
5
1
5
1
8.1. A register pair read operation is described in
N0.4
N1.4
C0.4
C1.4
Section
4
0
4
0
4
1
4
1
8.2.
N0.3
N1.3
C0.3
C1.3
3
0
3
0
3
1
3
1
2
C-bus/SMBus I/O expander
N0.2
N1.2
C0.2
C1.2
PCAL6416A
2
0
2
0
2
1
2
1
Section
© NXP B.V. 2012. All rights reserved.
N0.1
N1.1
C0.1
C1.1
1
0
1
0
1
1
1
1
8.1. A
N0.0
N1.0
C0.0
C1.0
12 of 54
0
0
0
0
0
1
0
1