PCAL6416APW,118 NXP Semiconductors, PCAL6416APW,118 Datasheet - Page 27

• Manufacturer Part Number: PCAL6416APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL6416APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 200 mA
• Output Current: 25 mA
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
Table 30.
T
[1]
[2]
PCAL6416A
Product data sheet
Symbol
(dV/dt)
(dV/dt)
t
V
t
V
d(rst)
w(gl)VDD
amb
POR(trip)
DD(gl)
Level that V
Glitch width that will not cause a functional disruption when V
= 25
f
r

C (unless otherwise noted). Not tested; specified by design.
Recommended supply sequencing and ramp rates
Parameter
fall rate of change of voltage
rise rate of change of voltage
reset delay time
glitch supply voltage difference
supply voltage glitch pulse width
power-on reset trip voltage
DD(P)
can glitch down to with a ramp rate = 0.4 s/V, but not cause a functional disruption when t
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (t
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance.
how to measure these specifications.
V
is released and all the registers and the I
their default states. The value of V
0 V.
Fig 23. Glitch width and glitch height
Fig 24. Power-on reset voltage (V
POR
Figure 24
is critical to the power-on reset. V
and
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Table 30
Rev. 3 — 24 December 2012
Condition
Figure 21
Figure 21
Figure
V
Figure
drops to V
Figure 23
Figure 23
falling V
rising V
DD(P)
w(gl)VDD
Low-voltage translating 16-bit I
drops below 0.2 V or to V
21; re-ramp time when
22; re-ramp time when V
provide more details on this specification.
DD(P)
DD(P)
POR(min)
DD(gl)
) and glitch height (V
POR
POR
= 0.5  V
Figure 23
)
differs based on the V
 50 mV)
POR
2
C-bus/SMBus state machine are initialized to
is the voltage level at which the reset condition
DD(P)
and
.
Table 30
DD(P)
SS
)
DD(gl)
[1]
[2]
2
provide more information on
DD(P)
) are dependent on each
C-bus/SMBus I/O expander
Min
0.1
0.1
1
1
-
-
0.7
-
PCAL6416A
being lowered to or from
w(gl)VDD
Typ
-
-
-
-
-
-
-
-
© NXP B.V. 2012. All rights reserved.
< 1 s.
Max
2000
2000
-
-
1.0
10
-
1.4
002aag962
002aag963
27 of 54
Unit
ms
ms
s
s
V
s
V
V