MAX3891ECB-TD Maxim Integrated, MAX3891ECB-TD Datasheet
MAX3891ECB-TD
Specifications of MAX3891ECB-TD
Related parts for MAX3891ECB-TD
MAX3891ECB-TD Summary of contents
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... Parallel to 2.5Gbps Serial Conversion o Clock Synthesis for 2.5Gbps o Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) o Additional High-Speed Output for System Loopback Testing o Single-Ended PECL Data Inputs o Differential PECL Clock Inputs and Serial Data Outputs PART MAX3891ECB *EP = Exposed Pad ...
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Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs ABSOLUTE MAXIMUM RATINGS Terminal Voltage (with respect to GND) V ..................................................................-0.5V to +5.0V CC All Inputs, FIL+, FIL- .............................-0. Output Currents PECL Outputs (SDO±, SCLKO±, PCLKO±) ..................50mA ...
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Serializer, 3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs AC ELECTRICAL CHARACTERISTICS (V = +3.0V to +3.6V, PECL loads = 50Ω ± are +25°C and V = +3.3V, unless otherwise noted.) (Note ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs PIN NAME 1, 17, 33, 48, GND Ground 49 10, 13, 14, 19, 21, 23, 25, 27, 29, 31, V +3.3V Supply Voltage CC 32, 35, ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs PCLKO PCLKI PARALLEL INPUT DATA (PDI_) NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCKLO = (PCLK0+) - (PCLKO-). *PDI I5 = D15; PDI14 = D14 PDI0 = ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs PDI15 PECL PARALLEL PDI1 REGISTER PECL PDI0 PECL BUF PCLKI+ PECL PCLKI- RCLK+ PHASE/FREQ PECL DETECT RCLK- Figure 2. Functional Block Diagram Applications Information Setup and Hold Time Requirements The ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs The adjusted setup (t ) and hold-time (t SUADJ requirements become t ( (or t SUADJ HADJ SU PECL Input and Output Terminations It is important ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs OVERHEAD GENERATION PECL TERMINATIONS OVERHEAD GENERATION DC-COUPLING TO PECL OUTPUTS OVERHEAD GENERATION AC-COUPLING TO NON-PECL OUTPUTS Figure 3. Alternative PECL-Input Termination 8 _______________________________________________________________________________________________________ _______________________________________________________________________________________ Z = 50Ω ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs MAX3891 SCLKO+ OR SDO+ SCLKO- OR SDO- MAX3891 SCLKO+ OR SDO+ SCLKO- OR SDO- Figure 4. Alternative PECL-Output Termination V CC 50Ω GND Figure 5. Current-Mode Logic _______________________________________________________________________________________ 0.1µF Z ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs TERM 155MHz REFERENCE CLOCK INPUT TERM TERM TERM OVERHEAD GENERATION TERM TERM TERM TERM THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z THIS SYMBOL REPRESENTS A PECL TERMINATION ...
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Serializer,3.3V, 2.5Gbps, SDH/SONET, with Clock Synthesis and LVPECL Inputs ______________________________________________________________________________________ Package Information 11 ...
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... Maxim reserves the right to change the circuitry and specifications without notice at any time. implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © ...