MAX3891ECB-TD Maxim Integrated, MAX3891ECB-TD Datasheet - Page 4

• Manufacturer Part Number: MAX3891ECB-TD
• Description: Serializers & Deserializers - Serdes
• Manufacturer: Maxim Integrated
• Type: Serializerr

Specifications of MAX3891ECB-TD

• Data Rate: 2.5 Gbit/s
• Input Type: LVPECL
• Output Type: LVPECL
• Number Of Inputs: 16
• Number Of Outputs: 1
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TQFP-64 EP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage - Max: 3.6 V
• Supply Voltage - Min: 3 V

16:1 Serializer,3.3V, 2.5Gbps, SDH/SONET,
with Clock Synthesis and LVPECL Inputs
4
53, 56, 60, 64
44, 46, 50, 52
1, 17, 33, 48,
2, 5, 7, 10,
13, 14, 19,
21, 23, 25,
27, 29, 31,
32, 35, 37,
39, 41, 43,
45, 47, 51,
18, 20, 22,
24, 26, 28,
30, 34, 36,
38, 40, 42,
_______________________________________________________________________________________
49, 63
PIN
EP
11
12
15
16
54
55
57
58
59
61
62
3
4
6
8
9
CLKSET
SCLKO+ Positive PECL Serial Clock Output
PCLKO+
PDI15 to
Exposed
SCLKO-
PCLKO-
PCLKI+
SLBO+
RCLK+
PCLKI-
NAME
SLBO-
PDI0
RCLK-
SDO+
Pad
SDO-
GND
FIL+
SOS
V
FIL-
CC
Ground
+3.3V Supply Voltage
System Loopback Negative Output. Enabled when SOS is high.
System Loopback Positive Output. Enabled when SOS is high.
System Loopback Output Select, TTL Input. System loopback disabled when low.
Negative PECL Serial Clock Output
Negative PECL Serial Data Output
Positive PECL Serial Data Output
Positive PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs.
Note that data is updated on the positive transition of the PCLKI signal.
Negative PECL Parallel Clock Input. Connect the incoming parallel-clock signal to the PCLKI inputs.
Note that data is updated on the positive transition of the PCLKI signal.
Single-Ended PECL Parallel Data Inputs. Data is clocked on the PCLKI positive transition. PDI15 is
transmitted first.
Positive PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead
management circuit.
Negative PECL Parallel Clock Output. Use positive transition of PCLKO to clock the overhead
management circuit.
P osi ti ve Refer ence C l ock Inp ut. C onnect a PE C L-com pati bl e cr ystal reference cl ock to the RCLK inp uts.
N egati ve Refer ence C l ock Inp ut. C onnect a PE C L-com pati bl e cr ystal reference cl ock to the RCLK inp uts.
Reference Clock Rate Programming Pin:
Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-
Filter Capacitor Input. Connect a 0.33µF capacitor between FIL+ and FIL-
Ground. This must be soldered to a circuit board for proper electrical and thermal performance (see
exposed pad package information).
CLKSET = V
CLKSET = Open: Reference Clock Rate = 77.76MHz
CLKSET = 20kΩ to GND: Reference Clock Rate = 51.84MHz
CLKSET = GND: Reference Clock Rate = 38.88MHz
CC
: Reference Clock Rate = 155.52MHz
FUNCTION
Pin Description