L6564HTR STMicroelectronics, L6564HTR Datasheet - Page 7

• Manufacturer Part Number: L6564HTR
• Description: Power Factor Correction ICs High Volt Start Up 700V PFC 100uA 6mA
• Manufacturer: STMicroelectronics

Specifications of L6564HTR

• Product Category: Power Factor Correction ICs
• Rohs: yes
• Maximum Power Dissipation: 0.75 W
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SO-14
• Minimum Operating Temperature: - 25 C

L6564H
3
Table 3.
n°
1
2
3
4
5
COMP
Name
MULT
VFF
INV
CS
Pin connection
Figure 2.
Pin description
Inverting input of the error amplifier. The information on the output voltage of the PFC pre-
regulator is fed into the pin through a resistor divider. The pin normally features high
impedance.
Output of the error amplifier. A compensation network is placed between this pin and INV (pin
1) to achieve stability of the voltage control loop and ensure high power factor and low THD. To
avoid an uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls
below 2.4 V the gate driver output is inhibited (burst-mode operation).
Main input to the multiplier. This pin is connected to the rectified mains voltage via a resistor
divider and provides the sinusoidal reference to the current loop. The voltage on this pin is used
also to derive the information on the RMS mains voltage.
Input to the PWM comparator. The current flowing in the MOSFET is sensed through a resistor,
the resulting voltage is applied to this pin and compared with an internal reference to determine
MOSFET turn-off. A second comparison level at 1.7 V detects abnormal currents (e.g. due to
boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily
stops the converter and limits the stress of the power components.
Second input to the multiplier for 1/V
connected from the pin to GND. They complete the internal peak-holding circuit that derives the
information on the RMS mains voltage. The voltage at this pin, a DC level equal to the peak
voltage on the MULT pin (3), compensates the control loop gain dependence on the mains
voltage. Never connect the pin directly to GND but with a resistor ranging from 100 KΩ
(minimum) to 2 MΩ (maximum).
Pin connection
PFC_OK
COMP
MULT
VFF
N.C.
INV
Doc ID 022960 Rev 2
CS
1
2
3
4
5
6
7
2
function. A capacitor and a parallel resistor must be
Function
10
14
11
13
12
9
8
Vcc
GD
GND
N.C.
HVS
ZCD
N.C.
Pin connection
AM11476v1
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