MCIMX6U5DVM10AB Freescale Semiconductor, MCIMX6U5DVM10AB Datasheet - Page 100

• Manufacturer Part Number: MCIMX6U5DVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
4.11.10.2.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in
Section 4.11.10.2.2, “Gated Clock
Mode,”)
except for the SENSB_HSYNC signal, which is not used (see
Figure
63). All incoming pixel clocks are
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
Start of Frame
nth frame
n+1th frame
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_DATA[19:0]
invalid
invalid
1st byte
1st byte
Figure 63. Non-Gated Clock Mode Timing Diagram
The timing described in
Figure 63
is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
100
Freescale Semiconductor