MCIMX6U5DVM10AB Freescale Semiconductor, MCIMX6U5DVM10AB Datasheet - Page 38

• Manufacturer Part Number: MCIMX6U5DVM10AB
• Description: Processors - Application Specialized i.MX6 DualLite
• Manufacturer: Freescale Semiconductor
• Type: Multimedia Applicationsr

Specifications of MCIMX6U5DVM10AB

• Rohs: yes
• Core: ARM Cortex A9
• Processor Series: i.MX6
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 1 GHz
• Data Ram Size: 256 kB
• Operating Supply Voltage: 1.175 V to 1.5 V
• Mounting Style: SMD/SMT
• Package / Case: FCBGA-624
• Interface Type: I2C, I2S, SDIO, UART, USB
• Memory Type: L1/L2 Cache, ROM, SRAM

Electrical Characteristics
4.6.2
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.
4.6.2.1
The LPDDR2 interface mode fully complies with JESD209-2B LPDDR2 JEDEC standard release June,
2009.
38
1
2
3
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below
0.6 V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot
must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or
other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
Pull-down resistor (100_kΩ PD)
Pull-down resistor (100_kΩ PD)
Input Hysteresis(OVDD= 1.8V)
Input Hysteresis(OVDD=3.3V
Pull-up resistor (100_kΩ PU)
Pull-up resistor (100_kΩ PU)
Pull-up resistor (22_kΩ PU)
Pull-up resistor (22_kΩ PU)
Pull-up resistor (47_kΩ PU)
Pull-up resistor (47_kΩ PU)
Low-Level input voltage
Keeper Circuit Resistance
Input current (no PU/PD)
High-level output voltage
Schmitt trigger VT+
Low-level output voltage
Input Reference Voltage
Schmitt trigger VT-
DDR I/O DC Parameters
LPDDR2 Mode I/O DC Parameters
Parameters
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 1
2,3
2,3
1,2
Table 24. LPDDR2 I/O DC Electrical Parameters
Table 23. GPIO DC Parameters (continued)
VHYS_HighVDD
VHYS_LowVDD
RPU_100K
RPU_100K
RPD_100K
RPD_100K
RPU_22K
RPU_22K
RPU_47K
RPU_47K
R_Keeper
Symbol
VTH+
VOH
VTH-
VOL
Vref
VIL
IIN
Test Conditions
VI =.3*OVDD, VI = .7* OVDD
Ioh= -0.1mA
Iol= 0.1mA
VI = 0, VI = OVDD
OVDD=1.8V
OVDD=3.3V
Vin=oOVDD
Vin=OVDD
Vin=OVDD
Vin=OVDD
Vin=0V
Vin=0V
Vin=0V
Vin=0V
0.49*OVDD
0.9*OVDD
Min
1
0.5*OVD
250
250
105
-1
D
0
Freescale Semiconductor
0.51*OVDD
0.1*OVDD
0.3*OVD
0.5*OVD
Max
212
100
175
48
48
D
D
1
1
1
1
1
mV
mV
mV
mV
kΩ
uA
uA
uA
uA
uA
uA
uA
uA
uA
V
Unit
V
V
V