MCIMX286CJM4A Freescale Semiconductor, MCIMX286CJM4A Datasheet

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... The integrated power management unit (PMU) on the i.MX28 is composed of a triple output DC-DC switching converter and multiple linear regulators. These provide power sequencing for the device and its I/O peripherals © 2012 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX28CEC Rev. 3, 07/2012 i.MX28 ...

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... Dual serial audio interface (SAIF) to support full-duplex transmit and receive operations; each SAIF supports three stereo pairs • Five application Universal Asynchronous Receiver-Transmitters (UARTs 3.25 Mbps with hardware flow control i.MX28 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...

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... MCIMX280DVM4B MCIMX280CVM4B MCIMX283DVM4B MCIMX283CVM4B MCIMX286DVM4B MCIMX286CVM4B MCIMX287CVM4B i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 1. Ordering Information – mm, 0.8mm pitch, MAPBGA-289 – mm, 0.8mm pitch, MAPBGA-289 – mm, 0.8 mm pitch, MAPBGA-289 – mm, 0.8 mm pitch, MAPBGA-289 – ...

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... OTG HS with HS PHY x1 HS Host with HS PHY x1 HS Host with HS PHY x1 i.MX286 i.MX287 — Yes Yes Yes Yes Yes x4 x4 Yes Yes x4 x4 Yes Yes OTG HS with HS PHY x1 HS Host with HS PHY x1 Freescale Semiconductor ...

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... Block Diagram Figure 1 shows the simplified interface block diagram. Figure 1. i.MX28 Simplified Interface Block Diagram i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Introduction 5 ...

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... Universal Serial Bus (USB) i.MX28 Applications Processors for Consumer Products, Rev Table 3. i.MX28 Functions Yes 8-bit 4 dedicated / 8 with muxing 5 dedicated / 8 with muxing 4 dedicated / 5 with muxing 3 dedicated / 4 with muxing 1 dedicated / 2 with muxing bits Yes Yes MACs with switch 2 BGA289 Freescale Semiconductor ...

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... Data Security co-processor i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 4. i.MX28 Digital and Analog Modules memory-mapped I/O to the APB devices, as well a central DMA facility for devices on this bus. The bridge provides a peripheral attachment bus running on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is synchronous to HCLK, as compared to APBX, which runs on the crystal-derived XCLK ...

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... CPU in PIO or PIO queue modes. It supports both 7-bit and 10-bit device address in master mode, and has programmable 7-bit address in slave mode. collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or IRQ line of the ARM9 CPU Freescale Semiconductor ...

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... PXP Pixel Pipeline Multimedia i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Brief Description The LCDIF provides display data for external LCD panels from simple text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF supports all of these different interfaces by providing fully programmable functionality and sharing register space, FIFOs, and ALU resources at the same time ...

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... The integrated USB 2.0 PHY macrocells are capable of connecting to USB host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed (FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps. The integrated PHYs provide a standard UTM interface. The USB_DP and USB_DN pins connect directly to a USB connector. Freescale Semiconductor ...

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... DC absolute maximum operating conditions. • Stresses beyond those listed under damage to the device. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 5. The package contact assignment is found in Assignments.” Signal descriptions are provided in the reference Table 5. Signal Considerations ...

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... Table 7. Electrostatic Discharge Immunity Table 8. Min. Max. –0.3 4.242 DD4P2V –0.3 7.00 –0.3 6.00 –0.3 2.10 –0.3 1.575 –0.3 3.63 –0.3 3.63 –0.3 BATT –0.3 VDDIO+0.3 –0.3 3.63 –0.3 VDDIO+0.3 –40 125 Tested Level 2 kV 500 V Freescale Semiconductor Unit ° C ...

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... For applications powered by external 5V only, the Maximum Ambient Operating Temperature specified in achieved. Application developers need to do the worst-case power consumption estimation, and then calculate the Total On-chip Power Dissipation based on the equations specified in note 3 below. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol ...

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... Run IDD Test Case Table 12. Conditions Min 1.57 V — 3.62 V — 2.12 V — 1.92 V — 1.92 V — ≤ (Θ (MAX Min Typ Max >1 — — Min Max 0.00 0.30 0.65 1.50 (1.1 * VDDXTAL) + 2.45 0. Typ Max Unit 150 188 1.11 1.17 mA 1.01 1.08 mA μA 0.61 2.97 Freescale Semiconductor ) where: D Unit MΩ Unit ...

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... For a given output, it may be possible to achieve a maximum output current higher than that specified by ensuring the load on the other outputs is well below the maximum. 6 Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1 Untuned. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 13. Power Supply Characteristics DDM ...

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... HW_CLKCTRL CPUCLK / clk_p Frequency max (MHz 360 392. 454.73 HW_CLKCTRL AHBCLK / clk_h Frequency max (MHz 160 196 206 Freescale Semiconductor Supported DRAM DDR2 mDDR DDR2 mDDR DDR2 mDDR DDR2 mDDR DDR2 mDDR ...

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... Power Modes Table 20 describes the core, clock, and module settings for the different power modes of the processor. Core/Clock/Module ARM Core USB0 PLL (System PLL) OSC24M i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor VDDD (V) Brownout 1.450 1.350 1.250 Symbol I program ...

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... Substrate metal thicknesses: 0.016 mm • Substrate core thickness: 0.160 mm i.MX28 Applications Processors for Consumer Products, Rev Table 20. Power Mode Settings (continued) Offstate On Off On Off At least 100ms Figure 2. RESETN Timing Standby Run On/Off On/Off Table 21. These values are measured Freescale Semiconductor ...

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... The current values and the I-V curves of the I/O DC characteristics are estimated based on an overly conservative device model. They are updated upon the measurement results of the first silicon. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 21. Thermal Resistance Data Single layer board (1s) ...

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... High 15 Low 36 Medium 17 High 16 Max. VDDIO_EMI + 0.3 VREF – 0.125 — - 0.2 * VDDIO_EMI — — — — — — — — — — 1 Typ. (Ω) Max. (Ω Freescale Semiconductor Unit ...

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... Output voltage low (dc) 1 Output source current (dc) gpio Output sink current (dc) gpio Output source current (dc) gpio_clk Output sink current (dc) gpio_clk i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 1, 2 Max Load Symbol Min VIH 2 VIL — 0.8 × VDDIO ...

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... Symbol Min Rpu10k 8 Rpu47k 39 Min 0.7 × VDDIO18 — 0.8 * VDDIO18 — -2.2 -3.5 -4.0 3.3 7.0 7.5 -4.2 -6.0 6.8 11 Max Unit 12 kΩ 56 kΩ Max Unit VDDIO18 V 0.3 × VDDIO18 V — V 0.2 × VDDIO18 V — mA — mA — mA — mA — mA — mA — mA — mA — mA — kΩ 56 kΩ Freescale Semiconductor ...

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... GPIO AC timing and parameters. Parameters Symbol Duty cycle Fduty Output pad transition tpr times (maximum drive) i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Testpoint Testpoint Figure 4. Output Pad Transition Waveform Table 27. Base GPIO Test Voltage Test Capacitance — — ...

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... Unit Rise/Fall 1.02 1.08 2.34 2.38 ns 1.51 1.5 3.34 3.28 2.91 2.62 6.24 5.67 1.26 1.29 2.9 2.6 1.8 1.88 4 3.67 3.3 3.46 6.91 6.64 1.62 1.68 3.65 3.68 ns 2.55 2.45 5.59 5.37 5.42 4.62 11.46 10.01 1.95 2.12 4.43 4.25 2.96 3.21 6.36 6.25 5.89 6.39 12.02 12.18 1.39 1.25 0.53 0.52 V/ns 0.97 0.93 0.38 0.38 0.54 0.56 0.22 0.23 2.08 2.00 0.73 0.83 1.52 1.44 0.55 0.60 0.88 0.83 0.34 0.35 1.12 1.06 0.44 0.43 V/ns 0.75 0.76 0.31 0.31 0.39 0.44 0.16 0.18 1.71 1.67 0.62 0.69 1.20 1.15 0.45 0.49 0.65 0.62 0.26 0.27 1.17 1.13 0.47 0.46 V/ns 0.75 0.78 0.30 0.32 0.35 0.41 0.15 0.17 1.11 1.02 0.41 0.42 0.73 0.67 0.28 0.29 0.37 0.34 0.15 0.15 100 75 mV 100 50 Freescale Semiconductor Notes — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ...

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... Output pad transition tpr times (low drive) Output pad slew rate tps (maximum drive) Output pad slew rate tps (medium drive) i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 28. F-type GPIO Test Capacitance Min Rise/Fall Max Rise/Fall — — 1.7~1. 0.58 1.7~1. ...

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... Unit 1.51 0.59 0.63 ns 0.96 0.35 0.40 0.46 0.16 0.19 1.39 0.59 0.60 0.82 0.37 0.36 0.36 0.17 0.16 100 75 mV 100 50 Max Rise/Fall units — — % 0.52 1.08 1.12 ns 0.74 1.56 1.56 1.28 3.04 2.7 0.57 1.25 1.12 0.85 1.73 1.63 1.63 3.13 3.08 0.76 1.67 1.62 ns 1.14 2.64 2.41 2.2 5.61 4.62 0.89 1.83 1.72 1.41 2.77 2.69 3.03 5.59 5.72 2.19 0.94 0.91 ns 1.54 0.65 0.65 0.89 0.34 0.38 3.79 1.44 1.61 2.54 1.04 1.10 1.33 0.58 0.58 Freescale Semiconductor Notes — — — — — — — — Notes — — — — — — — — — — — — — — — — — — — ...

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... There is no sample and hold circuit in LRADC only for DC input voltage or ones with very small slope. 2 This comprises only the required initial dummy conversion cycle, NOT including the Analog part power-up time. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 29. CLK-Type GPIO (continued) Min Rise/Fall 1.7~1. ...

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... Applications Processors for Consumer Products, Rev Table 31. HSADC Electrical Specification Conditions AC Electrical Specification — — — DC Electrical Specification — — Min. Typ. Max. Unit — 0.5 — bits — — 2 MHz 1 sample cycles 0.5 — VDDA-0.5 V μA — 10 — — 0.5 1.2 LSB — 0.5 1.2 LSB Freescale Semiconductor ...

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... This Ethernet output clock tolerance specification is the contribution from the PLL only and assumes a perfect 24 MHz clock/crystal source with 0 ppm deviation. The 24 MHz crystal frequency tolerance/deviation should be added to this number for the total Ethernet clock output frequency tolerance. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 32. USB PLL Specifications Test Conditions Min — ...

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... CK high level width DDR3 CK low level width i.MX28 Applications Processors for Consumer Products, Rev DDR2 DDR5 DDR4 DDR5 bank row column Symbol Min. tCK 4.86 tCH 0.5 tCK –0.5 tCL 0.5 tCK –0.5 DDR3 DDR1 DDR5 bank Max. Unit — ns 0.5 tCK ns + 0.5 0.5 tCK ns + 0.5 Freescale Semiconductor ...

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... DQS falling edge from CK rising edge—hold time DDR12 DQS falling edge to CK rising edge—setup time DDR13 DQS output high pulse width DDR14 DQS output low pulse width i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol tIS tIH DDR10 DDR11 DDR13 d0 ...

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... Figure 7. DDR2 Input AC Timing Table 36. DDR2 Input AC Timing Description Symbol Min Max tDS 1/4 tCK 1/4 tCK –0.8 –0.5 tDH 1/4 tCK 1/4 tCK –0.8 –0 Symbol Min Max tDQSCK –0.5 0.5 tDQSQ 0.25 tCK 0.25 tCK –0.85 –0.5 tQH 0.25 tCK 0.25 tCK +0. Freescale Semiconductor Unit ns ns Unit ...

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... Ethernet transceiver. All signals are compatible with transceivers operating at a voltage of 3.3 V. The following subsections describe the timing for MII and RMII modes. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor DDR20 DDR22 DDR21 ...

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... ENET0_TX_CLK frequency. i.MX28 Applications Processors for Consumer Products, Rev Table 38 describes the timing parameters (M1–M4) shown Table 38. MII Receive Signal Timing 1 M4 Min. Max. Unit 5 — — ns 35% 65% ENET0_RX_CLK period 35% 65% ENET0_RX_CLK period Freescale Semiconductor ...

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... Table 40. MII Asynchronous Inputs Signal Timing ID Characteristic 1 M9 ENET0_CRS to ENET0_COL minimum pulse width 1 ENET0_COL has the same timing in 10-Mbit 7-wire interface mode. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 39 describes the timing parameters (M5–M8) shown Table 39. MII Transmit Signal Timing 1 Characteristic ...

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... ENET0_TX_EN, ENET0_TXD[1:0], ENET0_RXD[1:0] and ENET0_RX_ER. i.MX28 Applications Processors for Consumer Products, Rev Table 41 describes the timing parameters (M10–M15) M14 M15 M10 M11 M12 M13 Min. 0 — 40% 40% Max. Unit — — ns — ns 60% ENET0_MDC period 60% ENET0_MDC period Freescale Semiconductor ...

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... MHz. TRACECLK is the ETM_TCLK signal which can be made functional by using some IOMUX configurations. See the reference manual for detailed information. 3.5.5.1 TRACECLK Timing This section describes TRACECLK timings. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 42 describes the timing parameters (M16–M21) shown in the M16 M18 M19 ...

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... Applications Processors for Consumer Products, Rev Table 43 describes the timing parameters shown in the Table 43. TRACECLK Signal Timing 1 Characteristic Table 44. Trace Data Signal Timing 1 Characteristic Min. Max. Unit 3 — — — — ns 12.5 — ns Min. Max. Unit 2 — — ns Freescale Semiconductor ...

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... Figure 16 through Figure 19 show the FlexCAN timing, including timing of the standby and shutdown signals. TXD t ONTXD V DIFF RXD i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 45. Tx Pin Characteristics Symbol Min — Table 46. Rx Pin Characteristics Symbol Min. 0.8 × ...

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... Figure 19. Timing Diagram for FlexCAN Shutdown-to-Standby Signal i.MX28 Applications Processors for Consumer Products, Rev 0.75 CC Bus Externally Driven 1.1V t SBRXDL t DRXDL OFFSHDN ONSHDN Bus Externally 0.5V Driven SHDNSB 0. Freescale Semiconductor ...

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... CLE CEn WE ALE IO[7:0] Figure 20. Command Latch Cycle Timing Diagram CLE CEn WE ALE IO[7:0] Figure 21. Address Latch Cycle Timing Diagram i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor NF2 NF1 NF3 NF5 NF6 NF7 NF8 NF9 Command NF1 NF4 NF3 NF10 ...

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... Figure 22. Write Data Latch Cycle Timing Diagram CLE CEn RE RB IO[7:0] Figure 23. Read Data Latch Cycle Timing Diagram i.MX28 Applications Processors for Consumer Products, Rev NF1 NF3 NF10 NF11 NF5 NF6 NF8 NF9 Data to NF NF14 NF15 NF13 NF17 NF16 NF12 Data from NF NF7 Freescale Semiconductor ...

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... HW_GPMI_TIMING0_ADDRESS_SETUP,HW_GPMI_TIMING0_DATA_SETUP,HW_GPMI_TIMING0_DATA_HOLD, this AC timing depends on these registers’ setting. In the above table we use AS/DS/DH representing these settings each. 3)AS minimum value could be 0, while DS/DH minimum value is 1. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 47. NFC Timing Parameters Timing T = GPMI Clock Cycle Symbol Min ...

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... Cck = Capacitance load on DOTCK pad Cd = Capacitance load on DATA/CTRL pad Figure 24. LCD AC Output Timing Diagram DOTCK = T/2 – 1.97ns + 0.15*Cck – 0.19*Cd DOTCK = T/2 + 0.29ns + 0.09*Cd – 0.10*Cck DOTCK = T/2 – 2.09ns + 0.18*Cck – 0.19*Cd DOTCK = T/2 + 0.40ns + 0.09*Cd – 0.10*Cck lists the LCD module timing Description tDW = T – 1.45ns Freescale Semiconductor ...

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... No IC9) + data_setup_time (ID No IC7) = 1000 + 250 = 1250 ns (according to the standard-mode I specification) before the I2C_SCL line is released total capacitance of one bus line in pF. b i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor 2 C connection compliant with SDA and SCL signal timings module. ...

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... Applications Processors for Consumer Products, Rev describes the SJC timing parameters (SJ1–SJ13) indicated in the SJ1 SJ2 VM VIL Figure 26. Test Clock Input Timing Diagram SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid SJ2 VM SJ3 VIH SJ5 Freescale Semiconductor ...

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... TCK low to output data valid SJ7 TCK low to output high impedance SJ8 TMS, TDI data set-up time SJ9 TMS, TDI data hold time i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 29 ...

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... All Frequencies Min. — — 100 40 Table 51 lists the PWM timing characteristics Figure 30. PWM Timing Minimum — — — 15.77 Unit Max — ns — Maximum Unit 24MHz MHz — ns — ns 0.3 ns 0.3 ns 15.08 ns — ns Freescale Semiconductor ...

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... Clock fall time 3b Clock rise time 4a Output delay time 4b Output setup time PWMO = 30 pF PWM Source Clock PWM Output i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Figure 31. PWM Timing Minimum 1 0 6.813 24.432 — — — ...

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... Figure 33. SAIF Transmitter Timing Diagram i.MX28 Applications Processors for Consumer Products, Rev Minimum 1 24 20.99 21.01 — — — 15.92 SS1 SS5 SS4 SS6 SS11 SS8 SS10 SS13 Maximum Unit 24 MHz — ns — ns 0.3 ns 0.3 ns 15.23 ns — ns Table 54 describes the timing SS3 SS7 SS9 SS12 Freescale Semiconductor ...

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... Figure 34 shows the timing for the SAIF receiver with internal clock. parameters (SS1–SS17) shown in the figure. SS2 BITCLK LRCLK SDATA0-2 i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 54. SAIF Transmitter Timing Parameter SS1 SS5 SS4 SS14 SS16 SS17 Figure 34 ...

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... Figure 35. spdif_clk Timing Min. Max. 81.4 — 36.0 — — 6.0 36.0 — — 6.0 — 15.0 — 15.0 10.0 — 0.0 — Timing Parameter Range Min Max — 1.5 — 13.6 — 18.0 81.4 — 65.1 — 65.1 — Freescale Semiconductor Unit Unit ...

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... Clock Fall Time SSP Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SSP Output Delay SSP Input / Card Outputs CMD, DAT (Reference to CLK) i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 57 lists the SD/MMC4.3 timing characteristics. SD4 SD2 SD5 ...

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... MMC4.4 timing characteristics. Be aware SCK SD2 DAT0 DAT1 ...... DAT7 SD3 SD4 DAT0 DAT1 ...... DAT7 Figure 37. MMC4.4 Timing Symbols ISU t IH Min Max Unit 2.5 — ns 2.5 — ns SD1 SD2 ...... ...... Min Max Unit 0 52 MHz – 2.5 — ns 2.5 — ns Freescale Semiconductor ...

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... MS4 SCK BS(CMD) DATA (Output) DATA (Input) Figure 39. MS Serial Transfer Mode Timing Diagram i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor show the timing of the Memory Stick. MS1 80% 50% 20% MS2 MS3 MS5 Figure 38. MS Clock Time Waveforms MS1 ...

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... Symbol tCLKc tCLKwh tCLKwl tCLKr MS12 MS14 Min Max Unit 50 — — — ns — — — — — — ns — Min Max Unit 25 — — — ns — Freescale Semiconductor ...

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... CS6 SS n lag time (CS hold time) CS7 MOSI setup time CS8 MOSI hold time CS9 MISO setup time CS10 MISO hold time i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Symbol tCLKf tBSsu tBSh tDsu tDh tDd CS3 CS2 CS3 CS2 Figure 41 ...

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... Figure 43. UART Receive Timing Diagram Table 62 Possible Parity Bit Next Start STOP Bit 6 Bit 7 Par Bit Bit BIT UA1 UA1 Max baud_rate ref_clk Table 63 Possible Parity Bit Next Start STOP Bit 7 Bit 6 Par Bit Bit BIT UA2 UA2 Freescale Semiconductor Unit — ...

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... Maximum solder bump diameter measured parallel to datum A. • Datum A, the seating plane, is determined by the spherical crowns of the solder bumps. • Parallelism measurement excludes any effect of mark on top surface of package. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Table 63. UART Receive Timing Parameters Symbol 1 t 1/F Rbit ) tolerance in each bit ...

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... MAPBGA package. Table 64. MAPBGA Power and Ground Contact Assignments Contact Name VDDA1 C13 VDDD G12,G11,F10,F11,K12,F12,G10 VDDIO18 G8,F9,F8,G9 VDDIO33 H8,J8,N3,G3,E6,J9,J10,A7,E16 VDDIO33_EMI N17 VDDIO_EMI P11,R13,N13,N15,G17,M12,M10,G13,M11,L13,G15 i.MX28 Applications Processors for Consumer Products, Rev Figure 44. i.MX28 Production Package zzxz Contact Assignment Freescale Semiconductor ...

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... AUART3_RX M5 AUART3_TX L5 BATTERY A15 DCDC_BATT B15 DCDC_GND A17 DCDC_LN1 B17 DCDC_LP A16 i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Contact Assignment Contact Signal Name Assignment EMI_DQS1N J16 EMI_ODT0 R17 EMI_ODT1 T17 EMI_RASN R16 EMI_VREF0 ...

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... LRADC6 C14 PSWITCH A11 PWM0 K7 PWM1 L7 PWM2 K8 PWM3 E9 PWM4 E10 RESETN A14 RTC_XTALI D11 RTC_XTALO C11 SAIF0_BITCLK F7 SAIF0_LRCLK G6 SAIF0_MCLK G7 SAIF0_SDATA0 E7 SAIF1_SDATA0 E8 SPDIF D7 SSP0_CMD A4 SSP0_DATA0 B6 SSP0_DATA1 C6 SSP0_DATA2 D6 SSP0_DATA3 A5 SSP0_DATA4 B5 SSP0_DATA5 C5 SSP0_DATA6 D5 SSP0_DATA7 B4 SSP0_DETECT D10 SSP0_SCK A6 SSP1_CMD C1 SSP1_DATA0 D1 SSP1_DATA3 E1 SSP1_SCK B1 SSP2_MISO B3 Freescale Semiconductor ...

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... K16 EMI_DQS1 J17 4.4 i.MX280 Ball Map Table 66 shows the i.MX280 MAPBGA ball map. Table 66. 289-Pin i.MX280 MAPBGA Ball Map i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments Contact Signal Name Assignment JTAG_TRST D14 LCD_CS P5 LCD_D00 ...

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... Package Information and Contact Assignments Table 66. 289-Pin i.MX280 MAPBGA Ball Map (continued) i.MX28 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...

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... Table 66. 289-Pin i.MX280 MAPBGA Ball Map (continued) 4.5 i.MX283 Ball Map Table 67 shows the i.MX283 MAPBGA ball map. Table 67. 289-Pin i.MX283 MAPBGA Ball Map i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 65 ...

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... Package Information and Contact Assignments Table 67. 289-Pin i.MX283 MAPBGA Ball Map (continued) i.MX28 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...

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... Table 67. 289-Pin i.MX283 MAPBGA Ball Map (continued) 4.6 i.MX286 Ball Map Table 68 shows the i.MX286 MAPBGA ball map. Table 68. 289-Pin i.MX286 MAPBGA Ball Map i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 67 ...

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... Package Information and Contact Assignments Table 68. 289-Pin i.MX286 MAPBGA Ball Map (continued) i.MX28 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...

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... Table 68. 289-Pin i.MX286 MAPBGA Ball Map (continued) 4.7 i.MX287 Ball Map Table 69 shows the i.MX287 MAPBGA Ball Map. Table 69. 289-Pin i.MX287 MAPBGA Ball Map i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 69 ...

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... Package Information and Contact Assignments Table 69. 289-Pin i.MX287 MAPBGA Ball Map (continued) i.MX28 Applications Processors for Consumer Products, Rev Freescale Semiconductor ...

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... Table 69. 289-Pin i.MX287 MAPBGA Ball Map (continued) i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Package Information and Contact Assignments 71 ...

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... Electrical Specification” 28, updated the “DC Electrical Specification” updated the first paragraph. Table 43. Figure 15 and Table 44 13, updated BATT row. 13. 21. 22. 29. 30. Freescale Semiconductor 14. ...

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... Table 70. Document Revision History (continued) Rev. Date Number Rev. 0 09/2010 Initial release. i.MX28 Applications Processors for Consumer Products, Rev. 3 Freescale Semiconductor Substantive Change(s) Revision History 73 ...

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... Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...