M95320-WMN6TP STMicroelectronics, M95320-WMN6TP Datasheet - Page 22

• Manufacturer Part Number: M95320-WMN6TP
• Description: IC EEPROM 32KBIT 10MHZ 8SOIC
• Manufacturer: STMicroelectronics

Specifications of M95320-WMN6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 32K (4K x 8)
• Speed: 10MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Organization: 4096 x 8
• Interface Type: SPI
• Maximum Clock Frequency: 10 MHz
• Access Time: 40 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8694-2; M95320-WMN6TP

Instructions
6.6
Note:
22/44
Write to Memory Array (WRITE)
As shown in
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. In the case of
latched in, indicating that the instruction is being used to write a single byte. The self-timed
Write cycle starts from the rising edge of Chip Select (S), and continues for a period t
specified in
to 0.
If, though, Chip Select (S) continues to be driven low, as shown in
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 32 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Table 18
Figure
0
1
High Impedance
12, to send this instruction to the device, Chip Select (S) is first driven
Figure
to
2
Instruction
Table
3
W
4
12, this occurs after the eighth bit of the data byte has been
is internally executed as a sequence of two consecutive
20), at the end of which the Write in Progress (WIP) bit is reset
5
Doc ID 5711 Rev 12
6
7
15
8
Table
14 13
9 10
16-Bit Address
6, the most significant address bits are Don’t Care.
3
20 21 22 23 24 25 26 27
2
1
0
M95320, M95320-W, M95320-R
7
6
Figure
5
Data Byte
4
13, the next byte of
3
28 29 30
2
1
0
31
AI01795D
WC
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