M95320-W STMICROELECTRONICS [STMicroelectronics], M95320-W Datasheet
M95320-W
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M95320-W Summary of contents
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... Feature summary Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: – 4.5 to 5.5V for M95320 and M95640 – 2.5 to 5.5V for M95320-W and M95320-W – 1.8 to 5.5V for M95320-R and M95640-R 10MHz, 5MHz or 2MHz clock rates 5ms or 10ms Write Time Status Register ...
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... CC Operating supply voltage Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 M95320, M95640, M95320-x, M95640-x ...
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... M95320, M95640, M95320-x, M95640-x 6.4 Write Status Register (WRSR 6.5 Read from Memory Array (READ 6.6 Write to Memory Array (WRITE Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ...
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... Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 8. Operating conditions (M95320 and M95640 Table 9. Operating conditions (M95320-W and M95640- Table 10. Operating conditions (M95320-R and M95640- Table 11. AC measurement conditions Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 13. DC characteristics (M95320 and M95640, device grade Table 14 ...
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... M95320, M95640, M95320-x, M95640-x List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. 8 pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9 ...
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... These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The M95320, M95320-W and M95320-R are 32Kbit devices organized as 4096 x 8 bits. The M95640, M95640-W and M95640-R are 64Kbit devices organized as 8192 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in The device is selected when Chip Select (S) is taken Low ...
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... M95320, M95640, M95320-x, M95640-x Table 1. Signal names HOLD Serial Clock Serial data Input Serial data Output Chip Select Write Protect Hold Supply Voltage Ground Summary description 7/44 ...
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... Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either High or Low, and must be stable during all write operations. 8/44 M95320, M95640, M95320-x, M95640-x must be held stable and within the specified valid range: CC Table 13 ...
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... M95320, M95640, M95320-x, M95640-x 3 Connecting to the SPI bus These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes Low ...
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... Stand-by mode and not transferring data: C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) Figure 4. SPI modes supported CPOL CPHA 10/44 MSB M95320, M95640, M95320-x, M95640-x Figure 4, is the clock polarity when the MSB AI01438B ...
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... M95320, M95640, M95320-x, M95640-x 4 Operating features 4.1 Supply voltage (V 4.1.1 Operating supply voltage V Prior to selecting the memory and issuing instructions to it, a valid and stable V within the specified [V secure a stable DC supply voltage recommended to decouple the V suitable capacitor (usually of the order of 10nF to 100nF) close to the V pins ...
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... Serial Clock (C) being Low. Figure 5. Hold condition activation C HOLD 12/ soon specified in Table CC1 Hold Condition M95320, M95640, M95320-x, M95640-x drops from the normal CC Table 17. Figure 5). Hold Condition AI02029D ...
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... Section 6.3: Read Status Register (RDSR) Array Addresses Protected Protected Block M95640, M95640-W, M95640-R, M95640-S none none Upper quarter 1800h - 1FFFh Upper half 1000h - 1FFFh Whole memory 0000h - 1FFFh Operating features for a M95320, M95320-W, M95320-R, M95320-S none 0C00h - 0FFFh 0800h - 0FFFh 0000h - 0FFFh 13/44 ...
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... Memory organization The memory is organized as shown in Figure 6. Block diagram HOLD Address Register 14/44 Figure 6. High Voltage Control Logic I/O Shift Register and Counter M95320, M95640, M95320-x, M95640-x Generator Data Register Status Register 1 Page X Decoder Size of the Read only EEPROM area AI01272C ...
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... M95320, M95640, M95320-x, M95640-x 6 Instructions Each instruction starts with a single-byte code, as summarized invalid instruction is sent (one not contained in <Blue>Table 3.), the device automatically deselects itself. Table 3. Instruction set Instruction WREN WRDI RDSR WRSR READ Read from Memory Array WRITE 6.1 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction ...
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... The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events: Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Figure 8. Write Disable (WRDI) sequence 16/ send this instruction to the device, Chip Select (S) is driven Low Instruction D High Impedance Q M95320, M95640, M95320-x, M95640 AI03750D ...
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... M95320, M95640, M95320-x, M95640-x 6.3 Read Status Register (RDSR) The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device ...
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... Status Register (WRSR) instruction. The new, updated, values take effect at the moment of completion of the execution of Write Status Register (WRSR) instruction. 18/ Instruction Status Register Out MSB Figure 10. Table 4. M95320, M95640, M95320-x, M95640-x Status Register Out MSB ) is initiated AI02031E ...
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... M95320, M95640, M95320-x, M95640-x Table 5. Protection modes W SRWD Signal Bit defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... Address range bits Device Address Bits 1. b15 to b13 are Don’t Care on the 64 Kbit devices. b15 to b12 are Don’t Care on the 32 Kbit devices. Figure 10. Write Status Register (WRSR) sequence 20/44 M95320, M95640, M95320-x, M95640-x (1) 32 Kbit Devices A12- ...
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... M95320, M95640, M95320-x, M95640-x 6.5 Read from Memory Array (READ) As shown in Figure Low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). ...
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... Instruction 16-Bit Address High Impedance Table 6, the most significant address bits are Don’t Care. M95320, M95640, M95320-x, M95640-x (as specified in Table 18 to Table Figure 13, the next byte Data Byte ...
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... M95320, M95640, M95320-x, M95640-x Figure 13. Page Write (WRITE) sequence Depending on the memory size, as shown Instruction 16-Bit Address Data Byte 2 Data Byte ...
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... The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous power-down (they are non-volatile bits). 7.2 Initial delivery state The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0. 24/44 M95320, M95640, M95320-x, M95640-x ...
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... M95320, M95640, M95320-x, M95640-x 8 Maximum rating Stressing the device outside the ratings listed in the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability ...
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... Operating conditions (M95320 and M95640) Symbol V Supply Voltage CC Ambient Operating Temperature (Device Grade Ambient Operating Temperature (Device Grade 3) Table 9. Operating conditions (M95320-W and M95640-W) Symbol V Supply Voltage CC Ambient Operating Temperature (Device Grade Ambient Operating Temperature (Device Grade 3) Table 10. ...
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... Output Low Voltage OL (1) V Output High Voltage OH 1. For all 5V range devices, the device meets the output requirements for both TTL and CMOS standards. Table 14. DC characteristics (M95320 and M95640, device grade 3) Symbol Parameter I Input Leakage Current LI I Output Leakage Current ...
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... V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH Table 16. DC characteristics (M95320-W and M95640-W, device grade 3) Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I Supply Current CC I Supply Current (Standby CC1 ...
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... M95320, M95640, M95320-x, M95640-x Table 17. DC characteristics (M95320-R and M95640-R) Symbol I Input Leakage Current LI I Output Leakage Current LO I Supply Current CC I Supply Current (Standby) CC1 V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH 1 ...
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... DC and AC parameters Table 18. AC characteristics (M95320 and M95640, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... M95320, M95640, M95320-x, M95640-x Table 19. AC characteristics (M95320 and M95640, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH ...
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... DC and AC parameters Table 20. AC characteristics (M95320-W and M95640-W, device grade 6) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX ...
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... M95320, M95640, M95320-x, M95640-x Table 21. AC characteristics (M95320-W and M95640-W, device grade 3) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH ...
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... Clock Low Set-up Time before HOLD not Active Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Valid HOLD Low to Output High-Z Write Time M95320, M95640, M95320-x, M95640-x and Table 10 Min. Max. D. ...
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... M95320, M95640, M95320-x, M95640-x Table 23. AC characteristics (M95640-R) Symbol Alt SCK t t SLCH CSS1 t t SHCH CSS2 t t SHSL CHSH CSH t CHSL ( CLH ( CLL ( CLCH RC ( CHCL DVCH DSU t t CHDX DH t HHCH ...
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... DC and AC parameters Figure 15. Serial Input timing S tCHSL C tDVCH D Q Figure 16. Hold timing HOLD 36/44 M95320, M95640, M95320-x, M95640-x tSLCH tCHDX MSB IN High Impedance tHLCH tCLHL tHLQZ tSHSL tCHSH tSHCH tCHCL tCLCH LSB IN AI01447C tHHCH tCLHH tHHQV AI01448B ...
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... M95320, M95640, M95320-x, M95640-x Figure 17. Output timing S C tCLQV tCLQX tCLQX Q ADDR. D LSB IN tCH tCLQV tQLQH tQHQL DC and AC parameters tCL tSHQZ LSB OUT AI01449e 37/44 ...
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... Typ Min Max 1.75 0.10 0.25 1.25 0.28 0.48 0.17 0.23 0.10 4.90 4.80 5.00 6.00 5.80 6.20 3.90 3.80 4.00 1.27 – – 0.25 0.50 0° 8° 0.40 1.27 1.04 M95320, M95640, M95320-x, M95640 45˚ c 0.25 mm GAUGE PLANE SO-A inches Typ Min 0.004 0.049 0.011 0.007 0.193 0.189 0.236 0.228 0.154 0.150 0.050 – 0.010 0° 0.016 0.041 Max 0.069 0.010 ...
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... M95320, M95640, M95320-x, M95640-x Figure 19. TSSOP8 – 8 lead Thin Shrink Small Outline, package outline Drawing is not to scale. Table 25. TSSOP8 – 8 lead Thin Shrink Small Outline, package mechanical data Symbol millimeters Typ ...
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... N 40/ ddd millimeters Typ Min Max 0.55 0.50 0.60 0.00 0.05 0.25 0.20 0.30 2.00 1.55 1.65 0.05 3.00 0.15 0.25 0.50 – – 0.45 0.40 0.50 0.15 0.30 8 M95320, M95640, M95320-x, M95640 UFDFPN-01 inches Typ Min 0.022 0.020 0.000 0.010 0.008 0.079 0.061 0.118 0.006 0.020 – 0.018 0.016 0.012 8 Max 0.024 0.002 0.012 0.065 0.002 0.010 – ...
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... M95320, M95640, M95320-x, M95640-x 11 Part numbering Table 27. Ordering information scheme Example: Device Type M95 = SPI serial access EEPROM Device Function 640 = 64 Kbit (8192 x 8) 320 = 32 Kbit (4096 x 8) Operating Voltage blank = V = 4 2 1.8 to 5.5V CC Package MN = SO8 (150 mil width) ...
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... Table of contents, and Pb-free options added. V 3.1 V (min) and V (min) corrected (improved) to -0.45V I O 4.0 TSSOP8 connections added to DIP and SO connections M95320, M95640, M95320-x, M95640-x Changes , and specification of t and t LO DLDH changed to 50ns for the -V range. (min) improved to -0.45V IL DHDL ...
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... Table 28. Document revision history (continued) Date Revision 24-May-2005 07-Jul-2006 M95320-S and M95640-S root part numbers (1.65 to 5.5V Supply) and related characteristics added. 20MHz Clock rate added.TSSOP14 package removed and MLP8 package added. Description of Power On Reset: VCC Lock-Out Write Protect Product List summary table added. Absolute Maximum Ratings for 5 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 M95320, M95640, M95320-x, M95640-x Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www ...