M95128-RDW6TP STMicroelectronics, M95128-RDW6TP Datasheet - Page 21

• Manufacturer Part Number: M95128-RDW6TP
• Description: IC EEPROM 128KBIT 2MHZ 8TSSOP
• Manufacturer: STMicroelectronics

Specifications of M95128-RDW6TP

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 128K (16K x 8)
• Speed: 2MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Density: 128Kb
• Interface Type: Serial (SPI)
• Organization: 16Kx8
• Access Time (max): 150ns
• Frequency (max): 2MHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Package Type: TSSOP
• Operating Temp Range: -40C to 85C
• Supply Current: 3mA
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 8
• Maximum Clock Frequency: 2 MHz
• Access Time: 150 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8684-2; M95128-RDW6TP

M95128, M95128-W, M95128-R
5.6
Note:
Write to Memory Array (WRITE)
As shown in
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a
byte boundary of the input data. The self-timed write cycle, triggered by the rising edge of
Chip Select (S), continues for a period t
of which the Write in Progress (WIP) bit is reset to 0.
In the case of
has been latched in, indicating that the instruction is being used to write a single byte. If,
though, Chip Select (S) continues to be driven low, as shown in
input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If the number of data bytes sent to the device exceeds the page
boundary, the internal address counter rolls over to the beginning of the page, and the
previous data there are overwritten with the incoming data. (The page size of these devices
is 64 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
●
●
●
●
The self-timed write cycle t
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.
Figure 10. Byte Write (WRITE) sequence
1. The most significant address bits (b15, b14) are Don’t Care.
S
C
D
Q
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a write cycle is already in progress
if the device has not been deselected, by Chip Select (S) being driven high, at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in)
if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Figure
Figure
0
1
High Impedance
10, to send this instruction to the device, Chip Select (S) is first driven
2
10, Chip Select (S) is driven high after the eighth bit of the data byte
Instruction
3
4
W
is internally executed as a sequence of two consecutive
5
Doc ID 5798 Rev 13
6
7
15
8
WC
14 13
9 10
(as specified in
16-Bit Address
3
20 21 22 23 24 25 26 27
2
1
0
Table 16
7
6
Figure
5
to
Data Byte
4
Table
11., the next byte of
3
28 29 30
2
19.), at the end
1
Instructions
0
31
AI01795D
21/44