CY7C1356C-166AXC Cypress Semiconductor Corp, CY7C1356C-166AXC Datasheet - Page 12

• Manufacturer Part Number: CY7C1356C-166AXC
• Description: IC SRAM 9MBIT 166MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1356C-166AXC

• Memory Size: 9M (512K x 18)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 166MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3.5 ns
• Maximum Clock Frequency: 166 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 180 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 2
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2122; CY7C1356C-166AXC

IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354C/CY7C1356C incorporates a serial boundary
scan test access port (TAP) in the BGA package only. The TQFP
package does not offer this functionality. This part operates in
accordance with IEEE Standard 1149.1-1900, but does not have
the set of functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of the
SRAM. Note that the TAP controller functions in a manner that
does not conflict with the operation of other devices using 1149.1
fully compliant TAPs. The TAP operates using JEDEC-standard
3.3 V or 2.5 V I/O logic levels.
The CY7C1354C/CY7C1356C contains a TAP controller,
instruction register, boundary scan register, bypass register, and
ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(V
internally pulled up and may be unconnected. They may
alternately be connected to V
should be left unconnected. Upon power-up, the device comes
up in a reset state which does not interfere with the operation of
the device.
TAP Controller State Diagram
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Document Number: 38-05538 Rev. *L
SS
1
0
) to prevent clocking of the device. TDI and TMS are
TEST-LOGIC
RUN-TEST/
RESET
IDLE
0
1
1
0
CAPTURE-DR
UPDATE-DR
PAUSE-DR
DR-SCA N
SHIFT-DR
EXIT1-DR
EXIT2-DR
1
SELECT
0
0
1
0
1
1
DD
0
through a pull up resistor. TDO
1
1
0
0
1
0
CAPTURE-IR
UPDATE-IR
PAUSE-IR
1
IR-SCAN
SHIFT-IR
EXIT1-IR
EXIT2-IR
SELECT
0
0
1
0
1
1
0
1
1
0
0
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit (MSB) of
any register. (See the
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine. The output changes on the falling edge
of TCK. TDO is connected to the least significant bit (LSB) of any
register. (See the
TAP Controller Block Diagram
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (V
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TM S
TCK
TDI
Selection
Circuitry
TAP Controller State
CY7C1354C, CY7C1356C
TAP Controller Block
Boundary Scan Register
Identification Register
31
x
Instruction Register
TAP CONTROLLER
30
.
29
Bypass Register
.
.
.
.
.
.
.
2
2
2
1
1
1
0
0
0
0
Diagram.)
Diagram.)
Selection
Circuitry
DD
Page 12 of 32
) for five rising
TDO
[+] Feedback