CY7C1360C-200AXC Cypress Semiconductor Corp, CY7C1360C-200AXC Datasheet - Page 8

• Manufacturer Part Number: CY7C1360C-200AXC
• Description: IC SRAM 9MBIT 200MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1360C-200AXC

• Memory Size: 9M (256K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Access Time: 3 ns
• Maximum Clock Frequency: 200 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 220 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2126; CY7C1360C-200AXC

Pin Definitions
Document Number: 38-05540 Rev. *K
A
BW
BW
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
ZZ
DQs, DQP
V
V
V
V
MODE
Note
3. CE
0
DD
SS
SSQ
DDQ
, A
1
2
3
Name
A
C
[3]
, BW
, BW
1
3
, A
is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.
B
D
X
I/O power supply Power supply for the I/O circuitry.
asynchronous
asynchronous
Power supply
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
synchronous
I/O ground
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
clock
static
I/O-
I/O
Address inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE
are fed to the two-bit counter.
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (all bytes are written, regardless of the values on BW
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must
be asserted LOW to conduct a byte write.
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
sampled only when a new external address is loaded.
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
address is loaded.
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
connected for BGA. Where referenced, CE
BGA. CE
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
automatically increments the address in a burst cycle.
Address strobe from processor, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
A
is recognized. ASDP is ignored when CE
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device are captured in the address registers. A
A
is recognized.
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or
left floating. ZZ pin has an internal pull-down.
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the addresses presented during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQP
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
Selects burst order. When tied to GND selects linear burst sequence. When tied to V
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode pin has an internal pull-up.
0
0
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP
2
1
1
3
and CE
and CE
and CE
is sampled only when a new external address is loaded.
2
3
3
[3]
[3]
to select/deselect the device. Not available for AJ package version. Not
to select/deselect the device. ADSP is ignored if CE
to select/deselect the device. CE
X
are placed in a tristate condition.
Description
1
3
is deasserted HIGH.
[3]
is assumed active throughout this document for
1
, CE
2
2
, and CE
is sampled only when a new external
CY7C1360C, CY7C1362C
3
[3]
are sampled active. A
1
is HIGH. CE
X
and BWE).
DD
Page 8 of 34
1
or left
1
is
, A
1
1
,
,
0
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