CY7C1380D-167AXI Cypress Semiconductor Corp, CY7C1380D-167AXI Datasheet

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... Synchronous self-timed write ■ Asynchronous output enable ■ Single cycle chip deselect ■ CY7C1380D/CY7C1382D is available in JEDEC-standard ■ Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA package; CY7C1380F/CY7C1382F is available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA and 165-ball FBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan ■ ...

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... Logic Block Diagram – CY7C1380D/CY7C1380F A0, A1, A ADDRESS REGISTER MODE ADV CLK ADSC ADSP DQ DQP BYTE BW D WRITE REGISTER DQ DQP BYTE BW C WRITE REGISTER DQ DQP BYTE BW B WRITE REGISTER DQ DQP BYTE A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL Logic Block Diagram – CY7C1382D/CY7C1382F ...

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... Pin Configurations 100-Pin TQFP Pinout (3-Chip Enable) Figure 1. CY7C1380D, CY7C1380F(512K X 36) Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Figure 2. CY7C1382D, CY7C1382F (1M X 18) Page [+] Feedback ...

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... A A TMS TDI TCK TDO Figure 4. CY7C1382F ( ADSP ADSC ADV CLK BWE DQP MODE NC/36M A TMS TDI TCK TDO CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F DDQ A NC/576M A NC/1G DQP DDQ DDQ DDQ DQP NC/36M DDQ DDQ A NC/576M A NC/1G DQP DDQ DDQ DDQ ...

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... DDQ DDQ N DQP DDQ P NC NC/72M A R MODE NC/36M NC/288M NC/144M A CE2 DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ N DQP DDQ P NC NC/72M A R MODE NC/36M A Document #: 38-05543 Rev. *F Figure 5. CY7C1380D/CY7C1380F (512K x 36 BWE CLK TDO TDI TCK TMS Figure 6 ...

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... ADSP is ignored and CE to select or deselect the device select or deselect the device sampled only when a new external address deasserted HIGH. 1 are placed in a tri-state condition. X CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F [2] , and CE are sampled active. A1 and BWE HIGH sampled 1 1 ...

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... No Connects. 36M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. Document #: 38-05543 Rev This pin is not available on TQFP packages. SS CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F or left DD . This pin is not available This pin is not available on ...

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... Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. The CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F is a common I/O device, the output enable (OE) must be deserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers ...

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... Sleep mode standby current DDZZ t Device operation to ZZ ZZS t ZZ recovery time ZZREC t ZZ Active to sleep current ZZI t ZZ Inactive to exit sleep current RZZI Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Table 2. Interleaved Burst Address Table (MODE = Floating or VDD) First Second Address Address A1 ...

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... CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State L L-H Tri-State L-H Tri-State L L-H Tri-State L L Writes may occur only on subsequent clocks X Page [+] Feedback ...

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... Write Byte A – (DQ and DQP ) A A Write Byte B – (DQ and DQP ) B B Write Bytes B, A Write All Bytes Write All Bytes Note 9. Table only lists a partial listing of the byte write combinations. Any combination of BW Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F GW BWE ...

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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380D/CY7C1382D incorporates a serial boundary scan test access port (TAP).This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1380D/CY7C1382D contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register ...

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... It also places the instruction register between the TDI and TDO balls and enables Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power up or whenever the TAP controller is given a test logic reset state ...

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... These instructions are not implemented but are reserved for future use. Do not use these instructions CYC TL t TMSS t TMSH t TDIS t TDIH t TDOX DON’T CARE UNDEFINED [10, 11] Over the Operating Range Description /t = 1ns CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F t TDOV Min Max Unit MHz ...

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... DDQ V = 2.5V DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F to 2.5V SS 1.25V 50Ω TDO Ω 20pF O Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0 ...

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... Bit Size (x36 Description CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Description Describes the version number. Reserved for internal use. Defines the memory type and architecture. Defines the memory type and architecture. Defines the width and density. Allows unique identification of SRAM vendor. ...

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... BGA Boundary Scan Order Bit # Ball ID Bit # Notes 14. Balls which are NC (No Connect) are pre-set LOW. 15. Bit pre-set HIGH. Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D [14, 15] Ball ID Bit # Ball CY7C1380F, CY7C1382F Bit # Ball Internal Page [+] Feedback ...

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... K11 17 J11 18 M10 19 L10 20 K10 21 J10 H10 24 G11 25 F11 26 E11 27 D11 28 G10 29 F10 30 E10 Note 16. Bit pre-set HIGH. Document #: 38-05543 Rev. *F [14, 16] Bit # Ball ID 31 D10 32 C11 33 A11 34 B11 35 A10 36 B10 C10 CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Bit # Ball Internal Page [+] Feedback ...

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... V ≤ /2), undershoot: V (AC) > –2V (pulse width less than t CYC IL (min.) within 200 ms. During this time V < V and CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F + 0.5V DD Ambient DDQ Temperature 0°C to +70°C 3.3V –5%/+10% 2.5V – –40°C to +85°C Min Max Unit 3.135 3 ...

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... V = 3.3V 2.5V DDQ 5 100 TQFP Test Conditions Package Test conditions follow standard 28.66 test methods and procedures for measuring thermal 4.08 impedance, in accordance with EIA/JESD51. CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 119 BGA 165 FBGA Unit Package Package 119 BGA 165 FBGA Unit ...

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... R = 317Ω 3.3V V DDQ GND 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V DDQ GND 1538Ω INCLUDING JIG AND SCOPE (b) CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ (c) Page [+] Feedback ...

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... V “AC Test Loads and Waveforms” and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 200 MHz 167 MHz Unit Max Min Max ...

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... CO t OEHZ t OELZ t DOH Q(A2 BURST READ DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F A3 Burst continued with new base address Deselect cycle t CHZ Q( Q(A2) Q( Burst wraps around to its initial state is HIGH LOW HIGH ...

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... Document #: 38-05543 Rev. *F [26, 27] Figure 11. Write Cycle Timing ADSC extends burst t WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED LOW. X CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F t ADS t ADH A3 t WES t WEH t t ADVH ADVS D( D(A3 Extended BURST WRITE ...

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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 29 HIGH. Document #: 38-05543 Rev. *F [26, 28, 29 WES t WEH OELZ D(A3) Q(A4) Q(A4+1) Single WRITE BURST READ DON’T CARE UNDEFINED CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F A5 A6 D(A5) D(A6) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Page [+] Feedback ...

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... DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05543 Rev. *F [30, 31] Figure 13. ZZ Mode Timing ZZI I DDZZ High-Z DON’T CARE “Truth Table” on page 10 for all possible signal conditions to deselect the device. CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F t ZZREC t RZZI DESELECT or READ Only Page [+] Feedback ...

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... Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1382D-250BZI CY7C1380F-250BZI CY7C1382F-250BZI CY7C1380D-250BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1382D-250BZXI CY7C1380F-250BZXI CY7C1382F-250BZXI Document #: 38-05543 Rev. *F http://app.cypress.com/portal/server.pt?space=CommunityPage&control=SetCom- Part and Package Type CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F www.cypress.com and refer Operating Range Commercial Industrial Page [+] Feedback ...

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... CY7C1382F-200BGXI CY7C1380D-200BZI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1382D-200BZI CY7C1380F-200BZI CY7C1382F-200BZI CY7C1380D-200BZXI 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1382D-200BZXI CY7C1380F-200BZXI CY7C1382F-200BZXI Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F Part and Package Type Operating Range Commercial Industrial Page [+] Feedback ...

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... Fine-Pitch Ball Grid Array ( 1.4 mm) CY7C1382D-167BZC CY7C1380F-167BZC CY7C1382F-167BZC CY7C1380D-167BZXC 51-85180 165-ball Fine-Pitch Ball Grid Array ( 1.4 mm) Pb-Free CY7C1382D-167BZXC CY7C1380F-167BZXC CY7C1382F-167BZXC CY7C1380D-167AXI 51-85050 100-pin Thin Quad Flat Pack ( 1.4 mm) Pb-Free CY7C1382D-167AXI CY7C1380F-167AXI CY7C1382F-167AXI CY7C1380F-167BGI 51-85115 119-ball Ball Grid Array ( 2.4 mm) CY7C1382F-167BGI CY7C1380F-167BGXI 51-85115 119-ball Ball Grid Array ( ...

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... BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS A CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 1.40±0.05 12°±1° A ...

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... Package Diagrams (continued) Figure 15. 119-Ball BGA ( 2.4 mm) (51-85115) Document #: 38-05543 Rev. *F CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F 51-85115-*B Page [+] Feedback ...

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... PACKAGE WEIGHT : 0.475g SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE WEIGHT : 0.475g PACKAGE CODE : BB0AC JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F BOTTOM VIEW PIN 1 CORNER BOTTOM VIEW PIN 1 CORNER Ø0. Ø ...

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... Document History Page Document Title: CY7C1380D/CY7C1382D/CY7C1380F/CY7C1382F, 18-Mbit (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05543 Submission Orig. of REV. ECN NO. Date Change ** 254515 See ECN RKF *A 288531 See ECN SYT *B 326078 See ECN PCI *C 416321 See ECN NXR *D 475009 See ECN VKN ...

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... All products and company names mentioned in this document may be the trademarks of their respective holders. PSoC Solutions psoc.cypress.com General clocks.cypress.com Low Power/Low Voltage Precision Analog LCD Drive image.cypress.com CAN 2.0b USB Revised January 12, 2009 CY7C1380D, CY7C1382D CY7C1380F, CY7C1382F psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb Page [+] Feedback ...