CY7C1380D-167AXI Cypress Semiconductor Corp, CY7C1380D-167AXI Datasheet - Page 22

• Manufacturer Part Number: CY7C1380D-167AXI
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Synchronousr

Specifications of CY7C1380D-167AXI

• Memory Size: 18M (512K x 36)
• Package / Case: 100-LQFP
• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Access Time: 3.4 ns
• Maximum Clock Frequency: 167 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3.135 V
• Maximum Operating Current: 275 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Ports: 4
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-2144; CY7C1380D-167AXI

Switching Characteristics
Document #: 38-05543 Rev. *F
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Setup Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
Parameter
20. Timing reference level is 1.5V when V
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
22. This part has a voltage regulator internally; t
23. t
24. At any given voltage and temperature, t
25. This parameter is sampled and not 100% tested.
can be initiated.
mV from steady-state voltage.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Setup Before CLK Rise
ADSC, ADSP Setup Before CLK Rise
ADV Setup Before CLK Rise
GW, BWE, BW
Data Input Setup Before CLK Rise
Chip Enable SetUp Before CLK Rise
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
ADV Hold After CLK Rise
GW, BWE, BW
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
DD
OEHZ
(Typical) to the first Access
are specified with AC test conditions shown in part (b) of
DDQ
Description
X
X
[23, 24, 25]
OEHZ
[23, 24, 25]
Setup Before CLK Rise
Hold After CLK Rise
= 3.3V and is 1.25V when V
Over the Operating Range
POWER
is less than t
is the time that the power needs to be supplied above V
[23, 24, 25]
[23, 24, 25]
OELZ
[22]
and t
CHZ
DDQ
is less than t
= 2.5V.
[20, 21]
Min
4.0
1.7
1.7
1.0
1.0
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
1
0
250 MHz
“AC Test Loads and Waveforms”
CLZ
to eliminate bus contention between SRAMs when sharing the same
Max
2.6
2.6
2.6
2.6
Min
2.0
2.0
1.3
1.3
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
200 MHz
1
5
0
DD
(minimum) initially before a read or write operation
CY7C1380D, CY7C1382D
CY7C1380F, CY7C1382F
Max
3.0
3.0
3.0
3.0
on page 21. Transition is measured ± 200
Min
2.2
2.2
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
167 MHz
1
6
0
Max
3.4
3.4
3.4
3.4
Page 22 of 34
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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