CAT24C05YI-GT3 ON Semiconductor, CAT24C05YI-GT3 Datasheet - Page 6

• Manufacturer Part Number: CAT24C05YI-GT3
• Description: IC EEPROM 4KBIT 400KHZ 8TSSOP
• Manufacturer: ON Semiconductor

Specifications of CAT24C05YI-GT3

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (512 x 8)
• Speed: 400kHz
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-TSSOP
• Organization: 512 x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 900 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Current: 1 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 24C05YI-GT3; CAT24C05YI-GT3TR

Byte Write
condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge, the
Master sends the byte address that is to be written into the
address pointer of the CAT24C03/05. After receiving
another acknowledge from the Slave, the Master transmits
the data byte to be written into the addressed memory
location. The CAT24C03/05 device will acknowledge the
data byte and the Master generates the STOP condition, at
which time the device begins its internal Write cycle to
nonvolatile memory (Figure 6). While this internal cycle is
in progress (t
CAT24C03/05 will not respond to any request from the
Master device (Figure 7).
Page Write
write cycle, using the Page Write operation (Figure 8). The
Page Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating after
the data byte is transmitted, the Master is allowed to send up
to fifteen additional bytes. After each byte has been
transmitted the CAT24C03/05 will respond with an
acknowledge and internally increments the four low order
address bits. The high order bits that define the page address
remain unchanged. If the Master transmits more than sixteen
bytes prior to sending the STOP condition, the address
counter ‘wraps around’ to the beginning of page and
previously transmitted data will be overwritten. Once all
In Byte Write mode, the Master sends the START
The CAT24C03/05 writes up to 16 bytes of data in a single
WR
), the SDA output will be tri−stated and the
BUS ACTIVITY:
MASTER
SLAVE
S
R
S
T
A
T
Figure 6. Byte Write Sequence
ADDRESS
SLAVE
WRITE OPERATIONS
http://onsemi.com
A
C
K
6
ADDRESS
sixteen bytes are received and the STOP condition has been
sent by the Master, the internal Write cycle begins. At this
point all received data is written to the CAT24C03/05 in a
single write cycle.
Acknowledge Polling
take advantage of the typical write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation, the CAT24C03/05 initiates the internal write
cycle. The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24C03/05 is still
busy with the write operation, NoACK will be returned. If
the CAT24C03/05 has completed the internal write
operation, an ACK will be returned and the host can then
proceed with the next read or write operation.
Hardware Write Protection
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the operation of
the CAT24C03/05. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first data
byte (Figure 9). If the WP pin is HIGH during the strobe
interval, the CAT24C03/05 will not acknowledge the data
byte and the Write request will be rejected.
Delivery State
FFh.
a
BYTE
7
The acknowledge (ACK) polling routine can be used to
With the WP pin held HIGH, the upper half of memory is
The CAT24C03/05 is shipped erased, i.e., all bytes are
÷ a
0
C
A
K
d
BYTE
DATA
7
÷ d
0
A
C
K
P
O
S
T
P