M25PE80-VMN6TP NUMONYX, M25PE80-VMN6TP Datasheet - Page 65

• Manufacturer Part Number: M25PE80-VMN6TP
• Description: IC FLASH 8MBIT 75MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25PE80-VMN6TP

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 8M (1M x 8)
• Speed: 75MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Package: 8SOIC N
• Cell Type: NOR
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 256Byte x 4096
• Timing Type: Synchronous
• Interface Type: Serial-SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25PE80-VMN6TPTR

M25PE80
Table 32.
30-Nov-2006
15-Jan-2007
09-Apr-2008
Date
Document revision history (continued)
Version
5
6
7
Important note on page 6
VFQFPN8 and SO8W packages updated and SO8N (MN) package
added (see
Figure 4: Bus master and memory devices on the SPI bus
explanatory paragraph added.
Reset signal behavior specified in
Section 6.10: Page program
Section 6.14: Sector erase (SE)
Section 8: Reset
Table 26: Timings after a Reset Low pulse
Table 3: Not for new design: TY7 process only, software protection
scheme truth table (sectors 0 and 15)
Software protection scheme
process only in
added,
added,
Protection always prevails:
T
ratings
M25PE80 products processed in T9HX process added to datasheet:
– WP pin replaces TSL (T7Y technology), see
–
– subsector protection granularity removed in T9HX process, still exists in
–
– Status register
SPM2 description and
Protection
VFQFPN8 package specifications updated (see
small text changes.
Removed ‘low voltage’ from the title.
Updated the value for the maximum clock frequency (from 50 to 75 MHz)
through the document.
Added: QFN8L package,
(T9HX (0.11 µm
operation, T9HX (0.11 µm)
Package
Modified:
devices on the SPI
Applied Numonyx branding.
LEAD
(W) or top sector lock (TSL)
Write status register (WRSR)
added for T9HX process
T7Y process
Table 5: Memory organization
added and V
Table 11
Table 13
mechanical.
Table 20: DC
modes.
Section 12: Package
Table 8: Status register
applies to T7Y process only.
applies to T7Y process only.
process),
added,
BP2, BP1, BP0 bits
bus, and
IO
max changed in
Table 4: Protected area sizes
characteristics,
Table 25: Reset conditions
Table 21: DC characteristics (75 MHz operation
added.
Table 24: AC characteristics (75 MHz
applies to T7Y process only.
process), and ECOPACK® text in
(PP),
figure removed. B3 and b2 apply to T7Y
Section 6.3: Read identification
Changes
and
and
updated to show subsectors
mechanical).
Section 6.8: Read lock register
Section 6.12: Page erase (PE)
Subsector erase (SSE)
Section 6.15: Bulk erase
and
applies to T7Y process only.
Table 16: Absolute maximum
Table 4: Bus master and memory
format,
SRWD bit
added.
Table 12: Lock register in
Section 2.6: Write protect
Table 10: Lock registers
Table 27
added in
modified and
added.
Revision history
and
updated and
instructions
(RDID).
Section 4.8:
Section 12:
Figure
(BE).
(RDLR),
and
65/66
30).