DS28E04S-100+T Maxim Integrated Products, DS28E04S-100+T Datasheet - Page 6

• Manufacturer Part Number: DS28E04S-100+T
• Description: IC EEPROM 4KBIT 16SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS28E04S-100+T

• Format - Memory: EEPROMs - Serial
• Memory Type: EEPROM
• Memory Size: 4K (256 x 16)
• Interface: 1-Wire Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Speed: -

Figure 2. Hierarchical Structure for 1-Wire Protocol
64-BIT DEVICE ID NUMBER (NETWORK ADDRESS)
Each DS28E04-100 has a unique device ID number that is 64 bits long, as shown in Figure 3. The first 8 bits are a
1-Wire family code. The next 8 bits are an external address byte, of which the lower 7 bits are connected to the
address input pins A0 to A6. This allows the user to set a portion of the Device ID Number by connecting some of
these pins to GND (logic 0) or to V
number. Even if multiple DS28E04-100 are used in a 1-Wire network and all address inputs are wired to the same
state or left open (unconnected), the unique 40-bit serialization field will prevent any address conflict, allowing to
communicate with each device individually. The last 8 bits are a lasered CRC (Cyclic Redundancy Check) of the
first 56 bits, assuming that the address input pins A0 to A6 are at logic 1. The 1-Wire CRC is generated using a
polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X
X
document.
Figure 3. 64-Bit Device ID Number
4
+ 1. Further information on the Device ID CRC is found in section CRC Generation near the end of this
MSB
MSB
Command
Level:
8-Bit CRC
Commands (see Figure 14)
Commands (see Figure 9)
Code
Memory/Control Function
1-Wire ROM Function
DS28E04-Specific
LSB
MSB
40-Bit Lasered Serial Number
CC
(logic 1) or leaving them open (logic 1). The next 40 bits are a lasered serial
DS28E04-100
Available
Commands:
Read ROM
Match ROM
Search ROM
Conditional Search
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
PIO Access Read
PIO Access Write
PIO Access Pulse
Reset Act. Latch
Write Register
ROM
LSB
6 of 36
0
MSB
A
6
Address Input
8-Bit External
A
5
Data Field
Affected:
Device ID, RC-Flag
Device ID, RC-Flag
Device ID, RC-Flag
Device ID, RC-Flag, PIO Status,
RC-Flag
RC-Flag
RC-Flag, OD-Flag
Device ID, RC-Flag, OD-Flag
32-byte Scratchpad, Flags
32-byte Scratchpad
Data Memory, Register Page
Data Memory, Registers
PIO Pins
PIO Pins, Activity Latch
PIO Pins, Activity Latch
Activity Latch
Conditional Search and Control
A
4
cond. Search Settings
A
3
Registers
A
2
LSB MSB
A
1
A
0
8-Bit Family Code
(1Ch)
LSB
LSB
8
+ X
5
+