MT48V4M32LFF5-8:G Micron Technology Inc, MT48V4M32LFF5-8:G Datasheet - Page 33

• Manufacturer Part Number: MT48V4M32LFF5-8:G
• Description: IC SDRAM 128MBIT 125MHZ 90VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48V4M32LFF5-8:G

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 128M (4Mx32)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 90-VFBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 18:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. M 1/09 EN
READ-to-PRECHARGE
Notes:
COMMAND
COMMAND
1. Assumes
2. N + 3 is either the last data element of a BL = 4 or the last desired data element of a longer
3. DQM is LOW.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL - 1. This is shown in Figure 19 on page 34 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
COMMAND
ADDRESS
ADDRESS
ADDRESS
burst.
CLK
CLK
CLK
DQ
DQ
DQ
BANK a,
BANK a,
BANK a,
t
COL n
COL n
COL n
RAS(MIN) has been satisfied prior to the PRECHARGE command.
T0
T0
T0
READ
READ
READ
CL = 1
CL = 2
T1
T1
T1
NOP
NOP
NOP
D
CL = 3
OUT
n
T2
T2
T2
NOP
NOP
NOP
33
D
D
n + 1
OUT
OUT
n
T3
T3
T3
NOP
NOP
NOP
D
n + 2
D
D
n + 1
OUT
OUT
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
PRECHARGE
PRECHARGE
PRECHARGE
(a or all)
(a or all)
(a or all)
T4
BANK
T4
BANK
BANK
T4
TRANSITIONING DATA
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
128Mb: x16, x32 Mobile SDRAM
OUT
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
D
n + 2
n + 3
OUT
OUT
t RP
t RP
t RP
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
©2001 Micron Technology, Inc. All rights reserved.
BANK a,
BANK a,
BANK a,
ACTIVE
ACTIVE
ACTIVE
T7
T7
T7
DON’T CARE
ROW
ROW
ROW
READs