CY7C1021BV33-12ZC Cypress Semiconductor Corp, CY7C1021BV33-12ZC Datasheet - Page 4

• Manufacturer Part Number: CY7C1021BV33-12ZC
• Description: IC SRAM 1MBIT 12NS 44TSOP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1021BV33-12ZC

• Format - Memory: RAM
• Memory Type: SRAM - Asynchronous
• Memory Size: 1M (64K x 16)
• Speed: 12ns
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-TSOP II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1015

Switching Characteristics
Data Retention Characteristics
Document #: 38-05148 Rev. *A
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
Shaded areas contain advance information.
V
I
t
t
Notes:
Parameter
10. t
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
DBE
LZBE
HZBE
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
BW
CCDR
CDR
R
4.
5.
6.
7.
8.
9.
DR
[10]
Parameter
[9]
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
t
At any given temperature and voltage condition, t
The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
No input may exceed V
Tested initially and after any design or process changes that may affect these parameters.
OL
HZOE
r
< 3 ns for the -12 and -15 speeds. t
/I
OH
, t
and 30-pF load capacitance.
HZBE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
, t
HZCE
[7]
V
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
, and t
CC
HZWE
CC
for Data Retention
Description
+ 0.5V.
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
r
Description
< 5 ns for the -20 and slower speeds.
[6]
[4]
[5, 6]
[6]
[5, 6]
[5, 6]
Over the Operating Range
Over the Operating Range (L version only)
HZCE
Com’l
is less than t
Min.
7C1021BV-8
8
3
0
3
0
4
0
8
7
6
0
0
6
4
0
3
8
LZCE
Max.
V
CE > V
V
, t
12
IN
CC
8
8
4
4
4
4
4
HZOE
> V
= V
is less than t
CC
CC
Conditions
DR
7C1021BV-10
Min.
– 0.3V,
– 0.3V or V
10
10
3
0
3
0
0
8
7
0
0
8
6
0
3
8
= 2.0V,
LZOE
Max.
, and t
10
10
12
[8]
4
5
5
5
5
5
IN
< 0.3V
HZWE
is less than t
7C1021BV-12
Min.
12
12
3
0
3
0
0
9
8
0
0
8
6
0
3
8
Min.
2.0
t
RC
0
LZWE
Max.
12
12
12
CY7C1021BV33
6
6
6
6
6
6
for any given device.
7C1021BV-15
Min.
15
15
10
10
10
Max.
100
3
0
3
0
0
0
0
8
0
3
9
Max.
15
15
15
Page 4 of 11
7
7
7
7
7
7
Unit
ns
ns
V
A
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns