CY7C1339B-100AC Cypress Semiconductor Corp, CY7C1339B-100AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1339B-100AC
• Description: IC SRAM 4MBIT 100MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1339B-100AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 4M (128K x 32)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 3.15 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1092

Document #: 38-05141 Rev. *A
Linear Burst Sequence
ZZ Mode Electrical Characteristics
Cycle Descriptions
A
00
01
10
11
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Begin Write
Begin Write
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “Sleep”
Notes:
I
t
t
1.
2.
3.
DDZZ
ZZS
ZZREC
[1:0]
Address
Next Cycle
X = “Don't Care,” 1 = HIGH, 0 = LOW.
Write is defined by BWE, BW
The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
First
Parameter
A
01
10
11
00
[1:0]
Address
Second
None
None
None
None
None
External
External
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
External
Next
Next
Current
Current
None
Add. Used
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
[1, 2, 3]
[3:0]
, and GW. See Write Cycle Descriptions table.
A
10
11
00
01
[1:0]
Address
Third
ZZ
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Description
CE
A
11
00
01
10
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
0
0
[1:0]
3
Address
Fourth
CE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
1
2
CE
X
X
X
X
X
X
X
X
1
0
0
0
0
0
0
1
1
1
1
1
0
1
1
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
1
ZZ > V
ZZ > V
ZZ < 0.2V
Test Conditions
ADSP
X
X
X
X
X
X
X
X
X
0
0
1
1
0
1
1
1
1
1
1
1
1
1
DD
DD
– 0.2V
– 0.2V
ADSC
X
X
X
X
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
, CE
ADV
2
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
1
1
0
0
1
1
, CE
2t
Min.
CYC
3
, ADSP, and ADSC must
ZZREC
OE
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
CY7C1339B
2t
Max.
CYC
3
after the ZZ input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
DQ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
Page 6 of 17
X
X
X
X
X
X
Read
Read
Read
Read
Write
Write
Write
Write
Write
X
Read
Read
Read
Read
Read
Write
Write
Unit
mA
Write
ns
ns