M25P20-VMN6T NUMONYX, M25P20-VMN6T Datasheet - Page 11

• Manufacturer Part Number: M25P20-VMN6T
• Description: IC FLASH 2MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P20-VMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1623-2

INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none. Chip Select (S) must be
driven High after the last bit of the instruction se-
quence has been shifted in.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep
Power-down, and Read Electronic Signature
Table 4. Instruction Set
FAST_READ Read Data Bytes at Higher Speed
Instruction
WREN
WRSR
RDSR
READ
WRDI
RES
PP
SE
BE
DP
Write Enable
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
Page Program
Sector Erase
Bulk Erase
Deep Power-down
Release from Deep Power-down,
and Read Electronic Signature
Release from Deep Power-down
Description
Table
4..
One-byte Instruction Code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
1010 1011
(RES) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a
byte boundary, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses
after Chip Select (S) being driven Low is an exact
multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
ABh
0Bh
D8h
C7h
06h
04h
05h
01h
03h
02h
B9h
Address
Bytes
0
0
0
0
3
3
3
3
0
0
0
0
Dummy
Bytes
0
0
0
0
0
1
0
0
0
0
3
0
M25P20
1 to 256
Bytes
1 to
1 to
1 to
1 to
Data
0
0
1
0
0
0
0
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