M25P20-VMN6T NUMONYX, M25P20-VMN6T Datasheet - Page 25

• Manufacturer Part Number: M25P20-VMN6T
• Description: IC FLASH 2MBIT 50MHZ 8SOIC
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P20-VMN6T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 497-1623-2

POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
the voltage applied on V
correct value:
–
–
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while V
On Reset (POR) threshold voltage, V
ations are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of t
elapsed after the moment that V
V
the device is not guaranteed if, by this time, V
still below V
Program or Erase instructions should be sent until
the later of:
Figure 20. Power-up Timing
WI
V CC (max)
V CC (min)
V
delay of t
V
threshold. However, the correct operation of
CC
SS
(min) at Power-up, and then for a further
V WI
at Power-down
V CC
CC
VSL
Reset State
(min). No Write Status Register,
Device
of the
Program, Erase and Write Commands are Rejected by the Device
CC
CC
Chip Selection Not Allowed
) until V
is less than the Power
CC
CC
rises above the
WI
reaches the
– all oper-
PUW
CC
has
is
tPUW
tVSL
–
–
These values are specified in
If the delay, t
above V
READ instructions even if the t
fully elapsed.
At Power-up, the device is in the following state:
–
–
Normal precautions must be taken for supply rail
decoupling, to stabilize the V
vice in a system should have the V
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V
ing voltage, to below the Power On Reset (POR)
threshold voltage, V
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Read Access allowed
t
t
The device is in the Standby mode (not the
Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
PUW
VSL
after V
CC
after V
(min), the device can be selected for
VSL
CC
CC
, has elapsed, after V
passed the V
passed the V
WI
, all operations are disabled
CC
Device fully
accessible
drops from the operat-
CC
Table
PUW
CC
WI
supply. Each de-
time
(min) level
delay is not yet
threshold
CC
7..
CC
rail decou-
M25P20
has risen
AI04009C
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