CY7C1382C-167AC Cypress Semiconductor Corp, CY7C1382C-167AC Datasheet
CY7C1382C-167AC
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CY7C1382C-167AC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05237 Rev. *D Functional Description The CY7C1380C/CY7C1382C SRAM integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The ...
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... BYTE BW B WRITE REGISTER DQ DQP BYTE BW A WRITE REGISTER BWE GW ENABLE CE 1 REGISTER SLEEP ZZ CONTROL 2 Logic Block Diagram – CY7C1382C (1M x 18) ADDRESS A0, A1, A REGISTER MODE ADV CLK COUNTER AND CLR ADSC ADSP DQ DQP B, B WRITE REGISTER DQP WRITE REGISTER A BWE GW ENABLE ...
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... Document #: 38-05237 Rev. *D 100-pin TQFP Pinout DQP DDQ 4 DDQ SSQ 5 SSQ SSQ 10 SSQ DDQ 11 DDQ DDQ 20 DDQ SSQ 21 SSQ DQP SSQ 26 SSQ DDQ 27 DDQ DQP CY7C1380C CY7C1382C DDQ V 76 SSQ DQP SSQ 70 V DDQ CY7C1382C ( DDQ V 60 SSQ SSQ V 54 DDQ Page ...
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... Document #: 38-05237 Rev. *D 119-ball BGA (1 Chip Enable with JTAG) CY7C1380C (512K x 36 ADSP A A ADSC DQP ADV CLK BWE DQP MODE 72M TMS TDI TCK TDO CY7C1382C (512K x 18 ADSP ADSC ADV CLK BWE DQP MODE 36M A TMS TDI TCK TDO CY7C1380C CY7C1382C ...
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... V B DDQ DDQ DDQ N DQP DDQ 72M A R MODE NC / 36M A Document #: 38-05237 Rev. *D 165-ball fBGA CY7C1380C (512K x 36 BWE CLK TDI A1 TDO TCK TMS CY7C1382C ( BWE CLK TDI A1 TDO TCK TMS CY7C1380C CY7C1382C ADSC ADV 144M OE ADSP DQP SS DDQ DDQ ...
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... A6 Input- Synchronous F4 B8 Input- Asynchronous G4 A9 Input- Synchronous CY7C1380C CY7C1382C Description Address Inputs used to select one of the 256K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active [2] LOW, and and CE are sampled active. A1: A0 are fed to the two-bit counter. . ...
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... G7,H2,H5,H6, H7,J5,J6,J7, K5,K6,K7, L5,L6,L7, M5,M6,M7,N4, N8 CY7C1380C CY7C1382C Description Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized ...
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... H10, N2,N5,N7,N10 ,P1,A1,B11,P2 ,R2,N6 R7 CY7C1380C CY7C1382C Description Ground for the I/O circuitry. Power supply for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation ...
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... CY7C1382C:Pin Definitions Name TQFP BGA 37,36,32, P4,N4 33,34,35, A2,B2, 42,43,44, C2,R2, 45,46,47, T2,A3, 48,49,50, B3,C3, 80,81,82, T3,A5, 99,100 B5,C5, T5,A6, B6,C6, R6,T6 93,94 G3, BWE CLK [ [ ADV Document #: 38-05237 Rev. *D fBGA I/O R6,P6,A2, Input- Address Inputs used to select one of the 512K A10,A11, Synchronous address locations ...
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... CY7C1382C:Pin Definitions (continued) Name TQFP BGA 84 A4 ADSP P4 85 ADSC 58,59,62, P7,K7, DQs, 63,68,69, G7,E7, DQPs 72,73,8,9, F6,H6,L6,N6, 12,13,18, D1, 19,22,23, H1,L1, 74,24 N1,E2, G2,K2, M2,D6 15,41,65, C4,J2,J4,J6 17,40,67, D3,D5 E5,E3,F3,F5, G5, H3,H5, K3,K5,L3,M3, M5, N3,N5, P3,P5 V 5,10,21,26,55, - SSQ 60,71, 76 Document #: 38-05237 Rev. *D fBGA ...
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... CY7C1382C:Pin Definitions (continued) Name TQFP BGA V 4,11,20,27,54, A1,A7,F1,F7, DDQ 61,70, J1,J7,M1,M7, 77 U1,U7 MODE 31 R3 TDO - U5 TDI - U3 TMS - U2 TCK - U4 NC 1,2,3,6,7, B1,B7, 14,16,25, C1,C7, 28,29,30, D2,D4, 38,39, D7,E1, 51,52,53, E6,H2, 56,57,66, F2,G1, 75,78,79, G6,H7, 95,96 J3,J5,K1, K6,L4,L2,L7, M6, N2,L7,P1,P6, R1, R5,R7, T1,T4,U6 Document #: 38-05237 Rev. *D ...
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... The interleaved burst sequence is designed specif- ically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. CY7C1380C CY7C1382C ) input, will selectively write to only the desired , are all asserted active, and 1 ...
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... CY7C1380C CY7C1382C , ADSP, and ADSC must after the ZZ input ZZREC Min. Max. Unit 60mA CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State L-H Tri-State Tri-State L L-H Tri-State L L L-H Tri-State L L-H Tri-State ...
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... D D Write Bytes D, A Write Bytes D, B Write Bytes Write Bytes D, C Write Bytes Write Bytes Write All Bytes Write All Bytes [5] Truth Table for Read/Write Function (CY7C1382C) Read Read Write Byte A – and DQP ) A A Write Byte B – and DQP ) B ...
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... Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the CY7C1380C CY7C1382C 0 Bypass Register ...
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... CLK captured in the boundary scan register. Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. CY7C1380C CY7C1382C Unlike the SAMPLE/PRELOAD Page ...
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... Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE Symbol /t = 1ns CY7C1380C CY7C1382C TDOV t TDOX UNDEFINED [9, 10] Min Max t 100 TCYC ...
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... DDQ V = 2.5V DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1380C CY7C1382C V to 2.5V SS 1.25V 50Ω 50Ω 20pF O MIN MAX UNITS 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 0.3 ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1380C CY7C1382C DESCRIPTION Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor ...
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... BGA Boundary Scan Order BIT# BALL Document #: 38-05237 Rev. *D CY7C1380C (512K x 36) BIT Not Bonded (Preset CY7C1380C CY7C1382C BALL Internal Internal Page ...
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... Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Document #: 38-05237 Rev. *D CY7C1382C (1M x 18) BIT Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset to 0) ...
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... Boundary Scan Order CY7C1380C (512K x 36) BIT# BALL B10 9 A10 10 C11 11 E10 12 F10 13 G10 14 D10 15 D11 16 E11 17 F11 18 G11 19 H11 20 J10 21 K10 22 L10 23 M10 24 J11 25 K11 26 L11 27 M11 28 N11 29 R11 30 R10 P10 P11 Document #: 38-05237 Rev. *D BIT# BALL Internal CY7C1380C CY7C1382C Page ...
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... M10 23 Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset R11 29 R10 P10 P11 Document #: 38-05237 Rev. *D CY7C1382C (1M x 18) BIT Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset to 0) ...
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... MHz 6.0-ns cycle, 167 MHz 7.5-ns cycle, 133 MHz V = Max, Device Deselected, All speeds DD ≤ 0. > V – 0.3V DDQ CY7C1380C CY7C1382C Ambient Temperature 0°C to +70°C 3.3V – 5%/+10% 2.5V – -40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
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... DD IH Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. Test Conditions Package T = 25° MHz 3.3V 2.5V DDQ CY7C1380C CY7C1382C Min. Max. 105 100 /2). CYC and V < DDQ DD\ TQFP BGA fBGA Package ...
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... R = 317Ω 3.3V OUTPUT 351Ω INCLUDING JIG AND (b) SCOPE R = 1667Ω 2.5V V OUTPUT =1538Ω INCLUDING JIG AND (b) SCOPE CY7C1380C CY7C1382C ALL INPUT PULSES V DD 90% 90% 10% GND ≤ 1ns (c) ALL INPUT PULSES DD 90% 90% 10% GND ≤ 1ns (c) Page 10% ≤ 1ns 10% ≤ ...
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... V is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1380C CY7C1382C 200 MHz 167 MHz 133 MHz Min. Max Min. Max 7.5 2 ...
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... OEHZ t OELZ t DOH Q(A2) Q( Q(A1) DON’T CARE UNDEFINED is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1380C CY7C1382C A3 Burst continued with new base address Deselect cycle t CHZ Q( Q( Q(A2) Q( Burst wraps around to its initial state BURST READ is HIGH LOW HIGH ...
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... Data Out (Q) BURST READ Single WRITE Document #: 38-05237 Rev WES t WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1380C CY7C1382C ADSC extends burst t ADS t ADH A3 t WES t WEH t t ADVS ADVH D( D(A3 Extended BURST WRITE Page ...
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... The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC . 24 HIGH. Document #: 38-05237 Rev WES t WEH OELZ D(A3) t OEHZ Q(A4) Single WRITE DON’T CARE UNDEFINED CY7C1380C CY7C1382C A5 D(A5) D(A6) Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs Page ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 26. DQs are in high-Z when exiting ZZ sleep mode Document #: 38-05237 Rev DDZZ High-Z DON’T CARE CY7C1380C CY7C1382C t ZZREC t RZZI DESELECT or READ Only Page ...
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... CY7C1380C-225AC CY7C1382C-225AC CY7C1380C-225BGC CY7C1382C-225BGC CY7C1380C-225BZC CY7C1382C-225BZC 200 CY7C1380C-200AC CY7C1382C-200AC CY7C1380C-200BGC CY7C1382C-200BGC CY7C1380C-200BZC CY7C1382C-200BZC 167 CY7C1380C-167AC CY7C1382C-167AC CY7C1380C-167BGC CY7C1382C-167BGC CY7C1380C-167BZC CY7C1382C-167BZC 133 CY7C1380C-133AC 167 CY7C1380C-167AI CY7C1382C-167AI CY7C1380C-167BGI CY7C1382C-167BGI CY7C1380C-167BZI CY7C1382C-167BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. ...
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... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. DIMENSIONS ARE IN MILLIMETERS 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1380C CY7C1382C 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05237 Rev. *D 119-Lead PBGA ( 2.4 mm) BG119 CY7C1380C CY7C1382C 51-85115-*B Page ...
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... FBGA ( 1.2 mm) BB165A i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05237 Rev. *D CY7C1380C CY7C1382C 51-85122-*C Page ...
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... Document History Page Document Title: CY7C1380C/CY7C1382C 18-Mb (512K x 36/1M x 18) Pipelined SRAM Document Number: 38-05237 REV. ECN NO. Issue Date ** 116277 08/27/02 *A 121540 11/21/02 *B 121797 11/21/02 *C 128904 09/11/03 *D 206081 02/13/04 Document #: 38-05237 Rev. *D Orig. of Change Description of Change SKX New Data Sheet DSG Updated package diagrams 51-85115 (BG119) to rev ...