CY7C1382C-167AC Cypress Semiconductor Corp, CY7C1382C-167AC Datasheet - Page 10

• Manufacturer Part Number: CY7C1382C-167AC
• Description: IC SRAM 18MBIT 167MHZ 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1382C-167AC

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 18M (512K x 36)
• Speed: 167MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1543

Document #: 38-05237 Rev. *D
CY7C1382C:Pin Definitions
ADSP
ADSC
ZZ
DQs,
DQPs
V
V
V
DD
SS
SSQ
Name
5,10,21,26,55,
72,73,8,9,
58,59,62,
63,68,69,
12,13,18,
19,22,23,
15,41,65,
17,40,67,
60,71,
TQFP
74,24
84
85
64
91
90
76
F6,H6,L6,N6,
K3,K5,L3,M3,
E5,E3,F3,F5,
C4,J2,J4,J6,
G7,E7,
G2,K2,
M2,D6,
D3,D5,
H3,H5,
N3,N5,
P7,K7,
N1,E2,
H1,L1,
P3,P5
BGA
M5,
D1,
G5,
A4
P4
P2
R4
T7
-
(continued)
F11,G11,J1,K1
M5,M6,M7,N4,
H5,H6,H7,J5,J
,L1,M1,D2,E2,
H2,C4,C5,C6,
C7,C8,D5,D6,
D4,D8,E4,E8,
D7,E5,E6,E7,
G2,C11,N1
G5,G6,G7,
G4,G8,H4,
L8,M4,M8
K5,K6,K7,
K4,K8,L4,
F5,F6,F7,
L10,M10,
H8,J4,J8,
L5,L6,L7,
D11,E11,
J10,K10,
F4,F8,
fBGA
6,J7,
H11
F2,
B9
A8
N8
-
Asynchronous
Power Supply Power supply inputs to the core of the device.
Synchronous
Synchronous
Synchronous
I/O Ground
Ground
Input-
Input-
Input-
I/O-
I/O
Address Strobe from Processor, sampled on
the rising edge of CLK, active LOW. When
asserted LOW, addresses presented to the device
are captured in the address registers. A1: A0 are
also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ASDP is ignored when CE
Address Strobe from Controller, sampled on the
rising edge of CLK, active LOW. When asserted
LOW, addresses presented to the device are
captured in the address registers. A1: A0 are also
loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input, active HIGH. When asserted
HIGH places the device in a non-time-critical
“sleep” condition with data integrity preserved. For
normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed
into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data
contained in the memory location specified by the
addresses presented during the previous clock rise
of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the
pins behave as outputs. When HIGH, DQs and
DQP
Ground for the core of the device.
Ground for the I/O circuitry.
X
are placed in a tri-state condition.
Description
1
is deasserted HIGH.
CY7C1380C
CY7C1382C
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