DP8422AV-20 National Semiconductor, DP8422AV-20 Datasheet - Page 30

• Manufacturer Part Number: DP8422AV-20
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-20

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-20

6 0 Port A Wait State Support
6 4 GUARANTEEING RAS LOW TIME
AND RAS PRECHARGE TIME
The DP8420A 21A 22A will guarantee RAS precharge time
between accesses between refreshes and between ac-
cess and refreshes The programming bits R0 and R1 are
used to program combinations of RAS precharge time and
RAS low time referenced by positive edges of CLK RAS
low time is programmed for refreshes only During an ac-
cess the system designer guarantees the time RAS is as-
serted through the DP8420A 21A 22A wait logic Since in-
serting wait states into an access increases the length of
the CPU signals which are used to create ADS or ALE and
AREQ the time that RAS is asserted can be guaranteed
The
DP8420A 21A 22A Each RAS output has a separate posi-
precharge
FIGURE 25 Guaranteeing RAS Precharge (DTACK is Sampled at the ‘‘T2’’ Falling Clock Edge)
time
is
FIGURE 24b WAITIN Example (WAIT is Sampled at the End of ‘‘T2’’)
also
guaranteed
(Continued)
by
the
30
tive edge of CLK counter AREQ is negated setup to a posi-
tive edge of CLK to terminate the access That positive
edge is 1T The next positive edge is 2T RAS will not be
asserted until the programmed number of positive edges of
CLK have passed as shown in Figure 25 Once the pro-
grammed precharge time has been met RAS will be assert-
ed from the positive edge of CLK However since there is a
precharge counter per RAS an access using another RAS
will not be delayed Precharge time before a refresh is al-
ways referenced from the access RAS negating before
RAS0 for the refresh asserting After a refresh precharge
time is referenced from RAS3 negating for the refresh to
the access RAS asserting
TL F 8588 – C2
TL F 8588 – C3