DP8422AV-20 National Semiconductor, DP8422AV-20 Datasheet - Page 57

• Manufacturer Part Number: DP8422AV-20
• Description: IC CTRLR/DVR CMOS PROGRAM 84PLCC
• Manufacturer: National Semiconductor

Specifications of DP8422AV-20

• Controller Type: Dynamic RAM (DRAM)
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 84-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP8422AV-20

14 0 Functional Differences
between the DP8420A 21A 22A
and the DP8420 21 22
1 Extending the Column Address Strobe (CAS) after
2 Dual Accessing
3 Refresh Request Output (RFRQ)
4 Clearing the Refresh Request Clock Counter
15 0 DP8420A 21A 22A User Hints
1 All inputs to the DP8420A 21A 22A should be tied high
2 Each ground on the DP8420A 21A 22A must be decou-
3 The output called ‘‘CAP’’ should have a 0 1 F capacitor
4 The DP8420A 21A 22A has 20
AREQ Transitions High
The DP8420A 21A 22A allows CAS to be asserted for
an indefinite period of time beyond AREQ (or AREQB
DP8422A only Scrubbing refreshes are not affected ) be-
ing negated by continuing to assert the appropriate ECAS
inputs This feature is allowed as long as the ECAS0 input
was negated during programming The DP8420 21 22
does not allow this feature
The DP8420A 21A 22A asserts RAS either one or two
clock periods after GRANTB has been asserted or negat-
ed depending upon how the R0 bit was programmed dur-
ing the mode load operation The DP8420 21 22 will al-
ways start RAS one clock period after GRANTB is assert-
ed or negated The above statements assume that RAS
precharge has been completed by the time GRANTB is
asserted or negated
The DP8420A 21A 22A allows RFRQ (refresh request)
to be output on the WE output pin given that ECAS0 was
negated during programming or the controller was pro-
grammed to function in the address pipelining (memory
interleaving) mode
RFRQ to be output during the address pipelining mode
The DP8420A 21A 22A allows the internal refresh re-
quest clock counter to be cleared by negating DISRFSH
and asserting RFSH for at least 500 ns
DP8420 21 22 clears the internal refresh request clock
counter if DISRFSH remains low for at least 500 ns Once
the internal refresh request clock counter is cleared the
user is guaranteed that an internally generated RFRQ will
not be generated for at least 13
upon how programming bits C0 1 2 3 were pro-
grammed)
low or the output of some other device
Note One signal is active high COLINC (EXTNDRF) should be tied low
pled to the closest on-chip supply (V
ramic capacitor
grounds
DP8420A 21A 22A The decoupling capacitors should
be placed as close as possible with short leads to the
ground and supply pins of the DP8420A 21A 22A
to ground
tors built into the output drivers of RAS CAS address
and WE RFRQ Space should be provided for external
damping resistors on the printed circuit board (or wire-
to disable
are
This is necessary because these
kept
The DP8420 21 22 only allows
separate
series damping resis-
s–15
CC
) with 0 1 F ce-
inside
s (depending
The
the
57
5 The circuit board must have a good V
6 The traces from the DP8420A 21A 22A to the DRAM
7 ECAS0 should be held low during programming if the user
8 Parameter Changes due to Loading
9 It is required that the user perform a hardware reset of
be kept to less than 0 5V below ground by varying the
value of the damping resistor The damping resistors
should be placed as close as possible with short leads to
the driver outputs of the DP8420A 21A 22A
plane connection If the board is wire-wrapped the V
and ground pins of the DP8420A 21A 22A the DRAM
associated logic and buffer circuitry must be soldered to
the V
wishes that the DP8420A 21A 22A be compatible with a
DP8420 21 22 design
All A C parameters are specified with the equivalent load
capacitances including traces of 64 DRAMs organized
as 4 banks of 18 DRAMs each Maximums are based on
worst-case conditions If an output load changes then the
A C timing parameters associated with that particular
output must be changed For example if we changed our
output load to
C
C
we would have to modify some parameters (not all calcu-
lated here)
$308a clock to CAS asserted
(t
A ratio can be used to figure out the timing change per
change in capacitance for a particular parameter by using
the specifications and capacitances from heavy and light
load timing
Ratio
the DP8420A 21A 22A before programming and using
the chip A hardware reset consists of asserting both ML
and DISRFSH for a minimum of 16 positive edges of CLK
see Section 3 1
wrap board) because they may be needed The value of
these damping resistors (if needed) will vary depending
upon the output the capacitance of the load and the
characteristics of the trace as well as the routing of the
trace The value of the damping resistor also may vary
between the wire-wrap board and the printed circuit
board To determine the value of the series damping re-
sistor it is recommended to use an oscilloscope and look
at the furthest DRAM from the DP8420A 21A 22A The
undershoot of RAS CAS WE and the addresses should
should be as short as possible
$308a (actual)
RAH
e
e
250 pF loads on RAS0– 3 and CAS0–3
760 pF loads on Q0– 9 and WE
CC
e
e
e
and ground planes
$308a w Heavy Load
15 ns t
125 pF
79 ns
e
e
e
e
b
ASC
ratio)
b
(250 pF
(capacitance difference
11 7 ns
90 7 ns
72 ns
50 pF
C
e
H
a
(CAS)
0 ns)
$308a (specified)
b
e
a
250 pF load
125 pF)
75 pF
79 ns
7 ns
b
b
C
$308a w Light Load
L
(CAS)
75 pF
7 ns
CC
c
a
and ground
79 ns
CC