ADE7753ARS Analog Devices Inc, ADE7753ARS Datasheet - Page 17

• Manufacturer Part Number: ADE7753ARS
• Description: IC ENERGY METERING DETEC 20-SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7753ARS

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7753ZEB - BOARD EVALUATION AD7753

CHANNEL 2 ADC
Channel 2 Sampling
In Channel 2 waveform sampling mode (MODE[14:13] =
1,1 and WSMP = 1) the ADC output code scaling for
Channel 2 is not the same as Channel 1. Channel 2 waveform
sample is a 16-bit word and sign extended to 24 bits. For
normal operation, the differential voltage signal between
V2P and V2N should not exceed 0.5V. With maximum
voltage input (±0.5V at PGA gain of 1), the outputs from the
ADC swings between 2852h and D7AEh (±10,322 Deci-
mal). However, before being passed to the Waveform register,
the ADC output is passed through a single pole, low pass
filter with a cutoff frequency of 140Hz. The plots in Figure
24 shows the magnitude and phase response of this filter.
The LPF1 has the effect of attenuating the signal. For
example if the line frequency is 60Hz, then the signal at the
output of LPF1 will be attenuated by about 8%.
Note LPF1 does not affect the power calculation. The signal
processing chain in Channel 2 is illustrated in Figure 25.
Unlike Channel 1, Channel 2 has only one analog input range
(1V differential). However like Channel 1, Channel 2 does
have a PGA with gain selections of 1, 2, 4, 8 and 16. For
energy measurement, the output of the ADC is passed
REV. PrF 10/02
H(f)
0.5V, 0.25V, 0.125V,
62.5mV, 31.25mV
Analog
Input Range
Figure 25 – ADC and Signal Processing in Channel 2
Figure 24 – Magnitude & Phase response of LPF1
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
10
V2
1
1
0V
V1
V2P
V2N
60Hz
50 Hz, -19.7°
x1, x2, x4,
x8, x16
PGA2
1
GAIN[7:5]
140Hz
50 Hz, -0.52dB
60 Hz, -23.2°
2
REFERENCE
ADC 2
Frequency (Hz)
2.42V
0.919
60 Hz, -0.73dB
PRELIMINARY TECHNICAL DATA
DAE8h
D7AEh
10
2852h
2518h
0000h
2
LPF Output
word Range
0.73dB
LPF1
ENERGY CALCULATION
ACTIVE AND REACTIVE
VRMS CALCULATION
AND WAVEFORM
(PEAK/SAG/ZX)
SAMPLING
10
3
-10
-12
-14
-16
-18
-2
-4
-6
-8
0
–17–
directly to the multiplier and is not filtered. A HPF is not
required to remove any DC offset since it is only required to
remove the offset from one channel to eliminate errors due to
offsets in the power calculation. When in waveform sample
mode, one of four output sample rates can be chosen by using
bits 11 and 12 of the Mode register. The available output
sample rates are 27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—
see Mode Register. The interrupt request output IRQ signals a
sample availability by going active low. The timing is the
same as that for Channel 1 and is shown in Figure 22.
Channel 2 RMS calculation
Figure 26 shows the details of the signal processing chain for
the RMS calculation on Channel 2. The channel 2 RMS
value is processed from the samples used in the channel 2
waveform sampling mode. The RMS value will be slightly
attenuated because of LPF1. Channel 2 RMS value is stored
in the unsigned 24-bit VRMS register. The update rate of the
channel 2 RMS measurement is CLKIN/4.
With the specified full scale AC analog input signal of 0.5V,
the outputs from the LPF1 swings between 2518h and
DAE8h at 60 Hz- see Channel 2 ADC. The equivalent RMS
value of this full-scale AC signal is approximately 1,561,400
(17D338h) in the VRMS register.
Channel 2
Channel 2 RMS offset compensation
The ADE7753 incorporates a channel 2 RMS offset compen-
sation register (VRMSOS). This is a 12-bit signed registers
which can be used to remove offset in the channel 2 RMS
calculation. An offset may exist in the RMS calculation due
to input noises and dc offset in the input samples. The offset
calibration allows the contents of the VRMS register to be
maintained at zero when no voltage is applied.
1 LSB of the channel 2 RMS offset are equivalent to 1 LSB
of the RMS register. Assuming that the maximum value from
the channel 2 RMS calculation is 1,561,400d with full scale
AC inputs, then 1 LSB of the channel 2 RMS offset represents
0.064% of measurement error at -60dB down of full scale.
where V
tion.
PHASE COMPENSATION
When the HPF is disabled, the phase error between Channel
1 and Channel 2 is zero from DC to 3.5kHz. When HPF is
enabled, Channel 1 has a phase response illustrated in
Figures 28 & 29. Also shown in Figure 30 is the magnitude
response of the filter. As can be seen from the plots, the phase
response is almost zero from 45Hz to 1kHz, This is all that
is required in typical energy measurement applications.
V
rms
Figure 26 - Channel 2 RMS signal processing
rmso
V
rmso
LPF1
is the RMS measurement without offset correc-
Voltage Signal - V(t)
DAE8h
2518h
VRM SOS
0h
LPF3
SGN 2 9 2 8
VRMSOS[11:0]
ADE7753
+
+
S
2
2
2
1
2
0
17D338h
VRMS[23:0]
00h