ADE7753ARS Analog Devices Inc, ADE7753ARS Datasheet - Page 33

• Manufacturer Part Number: ADE7753ARS
• Description: IC ENERGY METERING DETEC 20-SSOP
• Manufacturer: Analog Devices Inc

Specifications of ADE7753ARS

• Rohs Status: RoHS non-compliant
• Input Impedance: 390 KOhm
• Measurement Error: 0.1%
• Voltage - I/o High: 2.4V
• Voltage - I/o Low: 0.8V
• Current - Supply: 3mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Meter Type: Single Phase
• For Use With: EVAL-ADE7753ZEB - BOARD EVALUATION AD7753

Mode Register (09H)
The ADE7753 functionality is configured by writing to the MODE register. Table VI below summarizes the functionality
of each bit in the MODE register .
Bit
Location
0
1
2
3
4
5
6
7
8
9
10
12, 11
14, 13
15
REV. PrF 10/02
(Wave form selection for sample mode)
(Short the analog inputs on Channel 2)
(Short the analog inputs on Channel 1)
(Waveform samples output data rate)
Bit
Mnemonic
D I S H P F
D I S L P F 2
D I S C F
D ISSAG
A S U S P E N D 0
T E M P S E L
SWRST
C Y C M O D E 0
D I S C H 1
D I S C H 2
SWAP
D T R T 1 , 0
WAVSEL1,0 00
POAM
(Positive Only Accumulation)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4 kSPS (CLKIN/256)
10 = 7.2 kSPS (CLKIN/512)
11 = 3.6 kSPS (CLKIN/1024)
(Swap CH1 & CH2 ADCs)
01= Reserved
00 = LPF2
WAVSEL
10 = CH1
11 = CH2
Default
Value
0
0
1
1
0
0
0
0
0
00
0
DISCH2
DISCH1
POAM
SWAP
DTRT
PRELIMINARY TECHNICAL DATA
*Register contents show power on defaults
Description
The HPF (High Pass Filter) in Channel 1 is disabled when this bit is set.
The LPF (Low Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.
The Frequency output CF is disabled when this bit is set
The line voltage Sag detection is disabled when this bit is set
By setting this bit to logic one, both ADE7753's A/D converters can be turned off. In
normal operation, this bit should be left at logic zero. All digital functionality can be
stopped by suspending the clock signal at CLKIN pin.
The Temperature conversion starts when this bit is set to one. This bit is automatically
reset to zero when the Temperature conversion is finished.
Software chip reset. A data transfer should not take place to the ADE7753 for at least 18µs
after a software reset.
Setting this bit to a logic one places the chip in line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to logic 1 the analog inputs V2P and V2N are connected to ADC 1 and
the analog inputs V1P and V1N are connected to ADC 2.
These bits are used to select the Waveform Register update rate
DTRT 1
0
0
1
1
These bits are used to select the source of the sampled data for the Waveform Register
WAVSEL1,0
0
0
1
1
Writing a logic one to this bit will allow only positive power to be accumulated in the
ADE7753. The default value of this bit is 0.
15
0
14
0
13
0
0
1
0
1
12
0
Table VI : Mode Register
11
0
D T R T 0
0
1
0
1
Length Source
24 bits Active Power signal (output of LPF2)
Reserved
24 bits Channel 1
24 bits Channel 2
10
0
MODE REGISTER*
0
9
–33–
8
0
0
7
0
6
Update Rate
27.9kSPS (CLKIN/128)
14kSPS (CLKIN/256)
7kSPS (CLKIN/512)
3.5kSPS (CLKIN/1024)
0
5
0
4
1
3
1
2
1
0
0
0
ADDR: 09H
DISHPF
(Disable HPF in Channel 1)
DISLPF2
(Disable LPF2 after multiplier)
DISCF
(Disable Frequency output CF)
DISSAG
(Disable SAG output)
ASUSPEND
(Suspend CH1&CH2 ADC’s)
STEMP
(Start temperature sensing)
SWRST
(Software chip reset)
CYCMODE
(Line Cycle Energy Accumulation Mode)
ADE7753