LT1641-2CS8#TRPBF Linear Technology, LT1641-2CS8#TRPBF Datasheet - Page 11

• Manufacturer Part Number: LT1641-2CS8#TRPBF
• Description: IC CONTRLR HOTSWAP POSVOLT 8SOIC
• Manufacturer: Linear Technology
• Type: Hot-Swap Controllerr

Specifications of LT1641-2CS8#TRPBF

• Applications: General Purpose
• Internal Switch(s): No
• Voltage - Supply: 9 V ~ 80 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Family Name: LT1641-2
• Package Type: SOIC N
• Operating Supply Voltage (min): 9V
• Operating Supply Voltage (max): 80V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Product Depth (mm): 3.99mm
• Product Height (mm): 1.5mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS compliant by exemption

APPLICATIO S I FOR ATIO
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
is recommended. The minimum trace width for 1oz cop-
per foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. 0.03" per amp or wider is recom-
mended. Note that 1oz copper exhibits a sheet resistance
of about 530µΩ/ . Small resistances add up quickly in
Figure 13. Gate Drive vs Supply Voltage
18
16
14
12
10
8
6
4
2
0
8
U
UV = 37V
48V
SHORT
V
GND
IN
10.2k
PIN
294k
13
1%
1%
R1
R2
U
V
CC
1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
(V)
TIMER
ON
18
V
CC
8
5
0.01Ω
W
R
C2
0.68µF
S
SENSE
23
7
LT1641-1
1641-1
10Ω
5%
Figure 12. Active Low Enable Module
R5
IRF530
F13
GATE
GND
Q1
1k, 5%
6
4
U
R6,
PWRGD
10nF
C1
D1
CMPZ
5248B
FB
2
3
MMBT5551LT1
high current applications. To improve noise immunity, put
the resistor divider to the ON pin close to the chip and keep
traces to V
ON pin to GND also helps reject induced noise. Figure 14
shows a layout that addresses these issues.
R3
143k
1%
R4
4.22k
1%
Figure 14. Recommended Layout for R1, R2 and R
R7
47k
5%
Q2
+
CC
and GND short. A 0.1µF capacitor from the
C
220µF
I
LOAD
L
R1
R2
LT1641-1/LT1641-2
ENABLE MODULE
V
ON/OFF
V
IN
IN
ACTIVE LOW
+
–
I
LOAD
V
V
OUT
OUT
LT1641-1
+
–
1641-1 F12
V
OUT
SENSE
RESISTOR, R
1641-1
F14
S
11
S
164112fc