PCA9624PW,118 NXP Semiconductors, PCA9624PW,118 Datasheet - Page 28

• Manufacturer Part Number: PCA9624PW,118
• Description: IC LED DRIVER RGBA 24-TSSOP
• Manufacturer: NXP Semiconductors
• Type: RGBA LED Driverr

Specifications of PCA9624PW,118

• Package / Case: 24-TSSOP
• Topology: Open Drain, PWM
• Number Of Outputs: 8
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: RGBA
• Frequency: 1MHz
• Voltage - Supply: 2.3 V ~ 5.5 V
• Voltage - Output: 40V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Current - Output / Channel: 100mA
• Internal Switch(s): Yes
• Low Level Output Current: 20 mA
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Supply Current: 10 mA
• Maximum Power Dissipation: 100 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Efficiency: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 03118 863 9352

NXP Semiconductors
[2]
[3]
[4]
[5]
[6]
PCA9624_2
Product data sheet
Fig 19. Definition of timing
Fig 20. I
t
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
bridge the undefined region of SCL’s falling edge.
The maximum t
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
C
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
VD;DAT
b
SDA
SCL
= total capacitance of one bus line in pF.
Rise and fall times refer to V
= minimum time for SDA data out to be valid following SCL LOW.
2
C-bus timing diagram
P
protocol
t
SDA
SCL
BUF
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (t
S
t
SU;STA
t
BUF
condition
t
START
HD;STA
t
LOW
(S)
t
HD;STA
IL
f
.
and V
t
LOW
t
r
t
t
r
HD;DAT
MSB
bit 7
(A7)
IH
t
.
HIGH
Rev. 02 — 26 August 2009
t
SU;DAT
t
f
t
1 / f
HIGH
bit 6
(A6)
SCL
t
t
HD;DAT
f
t
SU;DAT
bit 1
(D1)
t
VD;DAT
8-bit Fm+ I
Sr
(D0)
bit 0
t
SU;STA
t
t
VD;ACK
HD;STA
2
f
acknowledge
C-bus 100 mA 40 V LED driver
) for the SDA output stage is specified at
(A)
t
SU;STO
IL
of the SCL signal) in order to
002aab285
t
SP
condition
t
SU;STO
STOP
PCA9624
(P)
© NXP B.V. 2009. All rights reserved.
002aaa986
P
28 of 37