MAX7302ATE+T Maxim Integrated Products, MAX7302ATE+T Datasheet - Page 10

• Manufacturer Part Number: MAX7302ATE+T
• Description: IC LED DRIVER LINEAR 16-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Linear (I²C Interface)r

Specifications of MAX7302ATE+T

• Topology: Open Drain, PWM
• Number Of Outputs: 9
• Internal Driver: Yes
• Type - Primary: Backlight, LED Blinker
• Type - Secondary: White LED
• Frequency: 1MHz
• Voltage - Supply: 1.62 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Operating Temperature: -40°C ~ 125°C
• Current - Output / Channel: 25mA
• Internal Switch(s): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Output: -
• Efficiency: -
• Lead Free Status / Rohs Status: Details

SMBus/I
Level-Translating GPIO and LED Driver with CLA
The MAX7302 is set to one of four I
using the address input AD0 (see Table 5) and is
accessed over an I
400kHz. The MAX7302 slave address is determined on
each I
transmission is actually addressing the device. The
MAX7302 distinguishes whether address input AD0 is
connected to SDA, SCL, V
mission. Therefore, the MAX7302 slave address can be
configured dynamically in an application without tog-
gling the device supply.
The port I/O registers set the I/O ports, one register per
port (see Tables 6 and 7). Ports can be independently
configured as inputs or outputs (D7), push-pull or open
drain (D6). Port P1 can only be configured as an input or
an open-drain output. The push-pull bit (D6) setting for
the port I/O register P1 is ignored.
Configure a port as an input by writing a logic-high to
the MSB (bit D7) of the port I/O register (see Table 6).
See Figure 1 for input port structure. To obtain the logic
Table 5. Slave Address Selection
Table 6. Port I/O Registers (I/O Port Set as an Input, Registers 0x01/0x41 to 0x09/049)
10
CONNECTION
REGISTER BIT
______________________________________________________________________________________
GND
SCL
SDA
AD0
V
D4, D3
2
DD
C transmission, regardless of whether or not the
D7
D6
D5
D2
D1
D0
A6
1
1
1
1
2
Port transition state
2
Transition interrupt
C or SMBus serial interface up to
DESCRIPTION
C Interfaced 9-Port,
A5
Reserved bits
Port I/O set bit
0
0
0
0
Port supply
(read only)
Port status
(read only)
Debounce
reference
enable
DD
A4
DEVICE ADDRESS
0
0
0
0
, or GND during the trans-
A3
1
1
1
1
I/O Port Registers
2
C slave addresses,
A2
Slave Address
1
1
1
1
VALUE
A1
I/O Input Port
1
0
1
0
1
0
0
1
0
1
0
1
0
0
1
1
A0
0
1
0
1
Sets the I/O port as an input.
Refers the input to the V
Refers the input to the V
Disables the transition interrupt.
Enables the transition interrupt.
Do not write to these registers.
Disables debouncing of the input port.
Enables debouncing of the input port.
No transition has occurred since the last port read.
A transition has occurred since the last port read.
Port input is logic-low.
Port input is logic-high.
R
0
0 1
0 1
0 1
W
1
level of the port input, read the port I/O register bit, D0.
This readback value is the instantaneous logic level at
the time of the read request if debounce is disabled for
the port (port I/O register bit D2 = 0), or the debounced
result if debounce is enabled for the port (port I/O reg-
ister bit D2 = 1).
Configure a port as an output by writing a logic-low to the
MSB (bit D7) of the port I/O register. See Figures 2 and 3
for output port structure. The device reads back the logic
level, PWM, or the blink setting of the port (see Table 7).
The MAX7302 monitors the logic level of ports configured
as CLA outputs (see the Configurable Logic Array (CLA)
section).
The port supply, V
push-pull I/O ports. Ports P2–P9 can be configured as
push-pull I/O ports (see Figure 3). V
high port output voltage sourcing the logic-high port load
current. V
outputs and operates over a 1.62V to 5.5V voltage inde-
pendent of the MAX7302 power-supply voltage, V
Each port set as an input can be configured to switch
midrail of either the V
Whenever the port supply reference is changed from V
to V
transition flag on the port.
LA
, or vice versa, read the port register to clear any
LA
DD
Port Supplies and Level Translation
LA
supply voltage.
supply voltage.
provides level translation capability for the
FUNCTION
LA
, provides the logic supplies to all
DD
or the V
LA
LA
powers the logic-
I/O Output Port
port supplies.
DD
.
DD