IRS2166DSTRPBF International Rectifier, IRS2166DSTRPBF Datasheet - Page 12

• Manufacturer Part Number: IRS2166DSTRPBF
• Description: IC CTRL PFC/BALLAST 16-SOIC
• Manufacturer: International Rectifier
• Type: PFC/Ballast Controllerr

Specifications of IRS2166DSTRPBF

• Frequency: 40 ~ 46 kHz
• Current - Supply: 20mA
• Current - Output: 260mA
• Voltage - Supply: 12.5 V ~ 15.6 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• For Use With: IRPLLNR7 - KIT UNIV ELEC BALLAST FLUOR LAMP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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The PFC control circuit of the IRS2166D (Fig. 8) only
requires four control pins: VBUS, COMP, ZX and PFC.
The VBUS pin is for sensing the DC bus voltage (via an
external resistor voltage divider), the COMP pin programs
the on-time of M
the ZX pin detects when the inductor current discharges
to zero (via a secondary winding from the PFC inductor),
and the PFC pin is the low-side gate driver output for
M
The VBUS pin is regulated against a fixed internal 4.0 V
reference voltage (V
voltage (Fig. 9). The feedback loop is performed by an
operational transconductance amplifier (OTA) that sinks
or sources a current to the external capacitor at the
COMP pin. The resulting voltage on the COMP pin sets
the threshold for the charging of the internal timing
capacitor (C1) and therefore programs the on-time of
M
section, the gain of the OTA is set to a high level to raise
the DC bus level quickly and to minimize the transient on
the DC bus which can occur during ignition. During run
mode, the gain is then decreased to a lower level
necessary for achieving high power factor and low THD.
The off-time of M
L
is detected by a secondary winding on L
connected to the ZX pin.
exceeding the internal 2 V threshold (V
beginning of the off-time. A negative-going edge on the
ZX pin falling below (V
L
PFC
PFC
PFC
PFC
(+)
(-)
COMP
.
. During preheat and ignition modes of the ballast
current discharges to zero which signals the end of
VBUS
current to discharge to zero. This zero current level
Fig. 8: IRS2166D simplified PFC control circuit
Fig. 9: IRS2166D detailed PFC control circuit
RVBUS1
ZX
RVBUS
1
6
7
3.0V
7.6V
COMP2
4.0V
Run Mode Signal
GAIN
Discharge
2.0V
VCC to
UVLO-
PFC
OTA1
PFC
DCOMP
COMP
VBUS
COMP3
and the speed of the feedback loop,
M1
is determined by the time it takes the
BUSREG
CCOMP
4.3V
ZXTH+
C1
Control
PFC
COMP5
Fault Mode Signal
COMP4
LPFC
COM
M2
) for regulating the DC bus
- V
PFC
ZX
ZXHYS
R1
R2 Q
S
RS4
A positive-going edge
Q
S
R
RS3
) will occur when the
RZX
Q
Q
RPFC
ZXTH+
WATCH
TIMER
DOG
PFC
) signals the
MPFC
VCC
DFPC
which is
8
CBUS
PFC
the off-time and M
cycle repeats itself indefinitely until the PFC section is
disabled due to a fault detected by the ballast section
(fault mode), an over-voltage or undervoltage condition
on the DC bus, or, the negative transition of ZX pin
voltage does not occur. Should the negative edge on the
ZX pin not occur, M
timer forces a turn-on of M
programmed by the voltage on the COMP pin.
watch-dog pulses occur every 400 µs (t
until a correct positive- and negative-going signal is
detected on the ZX pin and normal PFC operation is
resumed.
A fixed on-time of M
input voltage produces a peak inductor current which
naturally follows the sinusoidal shape of the line input
voltage. The smoothed averaged line input current is in
phase with the line input voltage for high power factor but
the total harmonic distortion (THD), as well as the
individual higher harmonics, of the current can still be too
high. This is mostly due to cross-over distortion of the
line current near the zero-crossings of the line input
voltage. To achieve low harmonics which are acceptable
to international standard organizations and general
market requirements, an additional on-time modulation
circuit has been added to the PFC control. This circuit
dynamically increases the on-time of M
input voltage nears the zero-crossings (Fig. 11).
causes the peak L
line input current, to increase slightly higher near the
zero-crossings of the line input voltage. This reduces the
amount of cross-over distortion in the line input current
which reduces the THD and higher harmonics to low
levels.
Over-Voltage Protection (OVP)
Should over-voltage occur on the DC bus causing the
VBUS pin to exceed the internal 4.3 V threshold (V
the PFC output is disabled (set to a logic ‘low’). When the
DC bus decreases again causing the VBUS pin to
Fig. 10: LPFC current, PFC pin and ZX pin timing
I
PFC
LPFC
pin
pin
ZX
0
0
0
PFC
PFC
PFC
PFC
current, and therefore the smoothed
is turned on again (Fig. 10). The
will remain off until the watch-dog
diagram
over an entire cycle of the line
IRS2166D(S)PbF
PFC
for an on-time duration
PFC
WD
) indefinitely
as the line
BUSOV+
This
The
),
Page 12