IRS2168DSTRPBF International Rectifier, IRS2168DSTRPBF Datasheet - Page 14

• Manufacturer Part Number: IRS2168DSTRPBF
• Description: IC PFC & BALLAST CONTROL 16-SOIC
• Manufacturer: International Rectifier
• Type: PFC/Ballast Controllerr

Specifications of IRS2168DSTRPBF

• Frequency: 42.5 ~ 46.5 kHz
• Current - Supply: 10mA
• Current - Output: 260mA
• Voltage - Supply: 12.5 V ~ 15.6 V
• Operating Temperature: -25°C ~ 125°C
• Package / Case: 16-SOIC (3.9mm Width)
• For Use With: IRPLLNR5 - KIT BALLAST UNIV FLUOR 54W TL5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: IRS2168DSTRPBFTR

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Run Mode (RUN)
second time, the IC enters run mode. CPH continues to
charge up to V
minimum frequency (after the ignition ramp) and is
programmed by the external resistor (R
pin. Should hard-switching occur at the half-bridge at any
time (open-filament, lamp removal, etc.), the voltage
across the current sensing resistor (R
internal threshold of 1.2 V (V
will begin counting (see Fig. 5). Should the number of
consecutive over-current faults exceed 65 (n
IC will enter fault mode and the HO, LO and PFC gate
driver outputs will be latched low. During run mode, the
end-of-life (EOL) window comparator and the DC bus
undervoltage reset are both enabled.
DC Bus Undervoltage Reset
Should the DC bus decrease too low during a brown-out
line condition or over-load condition, the resonant output
stage to the lamp can shift near or below resonance. This
can produce hard switching at the half- bridge that can
damage the half-bridge switches, or, the DC bus can
decrease too far and the lamp can extinguish. To protect
against this, the V
reset threshold V
the voltage at the V
), V
down to the V
will be latched low.
designer should set the over-current limit of the PFC
section such that the DC bus does not drop until the AC
line input voltage falls below the minimum rated input
voltage of the ballast (see PFC section). When the PFC
over-current limit is correctly set, the DC bus voltage will
start to decrease when over-current is reached during
low-line conditions. The voltage measured at the V
will decrease below the internal 3.0 V threshold V
and the ballast will turn off cleanly. The pull-up resistor to
V
input line voltage increases high enough again where V
exceeds V
at the minimum specified ballast input voltage and the
PFC over-current should be set somewhere below this
level. This hysteresis will result in clean turn-on and turn-
off of the ballast.
CC
Once V
CC
(R
VCC
will be discharged through an internal MOSFET
) will then turn the ballast on again when the AC
CC
CCUV+
has exceeded 2/3*V
CCUV-
. R
CC
BUSUV-
.
BUS
VCC
BUS
threshold and all gate driver outputs
The operating frequency is at the
pin includes a 3.0 V undervoltage
. When the IC is in run mode and
should be set to turn the ballast on
pin decreases below 3.0 V (V
For proper ballast design, the
CSTH+
) and the fault counter
CC
CS
(V
FMIN
) will exceed the
CPHRUN+
) at the FMIN
EVENTS
) for the
BUS
), the
BUSUV-
BUSUV-
pin
CC
SD/EOL and CS Fault Mode
Should the voltage at the SD/EOL pin exceed 3.0 V
(V
mode, an end-of-life (EOL) fault condition has occurred
and the IC enters fault mode. LO, HO and PFC gate
driver outputs are all latched off in the ‘low’ state. CPH is
discharged to COM for resetting the preheat time and
VCO is discharged to COM for resetting the frequency.
To exit fault mode, V
(ballast power off) or the SD pin can be increased above
5.0 V (V
the IC to enter UVLO mode (see State Diagram, page 3).
Once V
pulled above 5.0 V (V
(lamp re-insertion), the IC will enter preheat mode and
begin oscillating again.
The current sense function will force the IC to enter fault
mode only after the voltage at the CS pin has been
greater than 1.2 V (V
cycles of LO. The voltage at the CS pin is AND-ed with
LO (see Fig. 9) so it will work with pulses that occur
during the LO on-time or DC. If the over-current faults
are not consecutive, then the internal fault counter will
count back down each cycle when there is no fault.
Should an over-current fault occur only for a few cycles
and then not occur again, the counter will eventually reset
to zero. The over-current fault counter is enabled during
preheat and run modes and disabled during ignition
mode.
EOLTH+)
CS
LO
1.25V
CC
SDTH+
Figure 9: Fault counter timing diagram
or decrease below 1.0 V (V
is above V
) (lamp removal). Either of these will force
Run or Preheat Mode
50 Cycles
SDTH+
CCUV+
CC
CSTH+
can be decreased below V
) and back below 3.0 V (V
) for 65 (n
(ballast power on) and SD is
IRS2168D(S)PbF
EVENTS
EOLTH-
Fault Mode
) consecutive
) during run
SDTH-
CCUV-
)
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