IR5001STRPBF International Rectifier, IR5001STRPBF Datasheet - Page 10

• Manufacturer Part Number: IR5001STRPBF
• Description: IC CTLR/MOSFET UNIV N-CH 8-SOIC
• Manufacturer: International Rectifier

Specifications of IR5001STRPBF

• Package / Case: 8-SOIC (3.9mm Width)
• Mounting Type: Surface Mount
• Current - Supply: 500µA
• Voltage - Supply: 36 V ~ 75 V
• Operating Temperature: 0°C ~ 85°C
• Applications: -48V Dist Power Systems, AdvancedTCA ® Systems
• Number Of Outputs: 1
• Internal Switch(s): No
• Fet Type: N-Channel
• Delay Time - On: 27µs
• Delay Time - Off: 130ns
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Package Type: SOIC N
• Screening Level: Automotive
• Device Type: O-Ring Controller / MOSFET Driver
• Input Delay: 27µs
• Output Delay: 130ns
• Driver Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• Package: 8-lead SOIC Narrow
• Input Voltage: 100V Max Continuous
• Vline: 36V to 75V 100V Max or 12Vreg
• Offset Voltage (v): -7.9mV min to 0V max
• Turn-on Time (ns): 20
• Turn-off Time (ns): 130
• T Off Gate Drive: 3A Peak
• Junction Temperature: -40oC to 125oC
• Special Ic: FetCheck Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATION INFORMATION
The IR5001S is designed for multiple active ORing
and reverse polarity protection applications with
minimal number of external components. Examples
of typical circuit connections are shown below.
Negative Rail ORing/Reverse Polarity Protection
rail Active ORing or reverse polarity protection is
shown in Fig. 17. In this example, IR5001S is biased
directly from the positive rail. However, any of the
biasing schemes shown in Fig. 16 can be used.
boards, one IR5001S is used per feed. This is
shown in Fig.1. An evaluation kit is available for
typical system boards, with input voltages of
negative 36V to negative 75V, and for power levels
from 30W to about 300W. The p/n for the evaluation
kit is IRDC5001-LS48V. This evaluation kit contains
detailed
performance data for the IR5001S.
Figure. 17 Connection of INN, INP, and Gnd for negative
rail Active ORing or reverse polarity protection.
Figure. 18. Connection of INN,INP, and Gnd when the
MOSFET is placed in the path of positive rail.
www.irf.com
Vin -
Vin +
Vbias
Vout +
Vout -
Vbias
A typical connection of the IR5001S in negative
For input ORing in carrier-class communications
+
+
Rbias
Rbias
design
Vline
Vcc
FETch
FETst
Vline
Vcc
FETst
FETch
considerations
IR5001
IR5001
OUT
Gnd
INN
OUT
INP
Gnd
INN
INP
and
Redundant Vout +
Redundant Vin -
in-circuit
Load
Load
Positive Rail ORing / Ground ORing in
Communications Boards
rail ORing is shown in Fig. 18. Typical applications
are inside redundant AC-DC and DC-DC power
supplies, or on-board ORing. For positive rail ORing,
an additional Vbias voltage above the positive rail is
needed to bias the IR5001S.
rail ORing is available under p/n IRAC5001-
HS100A,
IR5001S at 100A output current.
Considerations for the Selection of the Active
ORing N-Channel MOSFET
losses, and depend on the source-drain current and
R
virtually eliminated if a FET with very low R
was used. However, using arbitrarily low R
not desirable for three reasons:
1. Turn off propagation delay. Higher R
2. Undetected reverse (drain to source) current
3. Cost. With properly selected R
DS(on)
An example of a typical connection in positive
An evaluation kit for high-current 12V positive
Active ORing FET losses are all conduction
provide more voltage information to the internal
comparator, and will result in faster FET turn off
protection in case of short-circuit of the source
(less voltage disturbance on the redundant bus).
flow. With the asymmetrical offset voltage, some
small current can flow from the drain to source
of the ORing FET and be undetected by the
IR5001S. The amount of undetected drain-
source current depends on the R
selected MOSFET and its R
reverse (drain-source) current below 5 – 10% of
the nominal source-drain state, the R
the selected FET should produce 50mV to
100mV of the voltage drop during nominal
operation.
ORing using IR5001S can be very cost
competitive
providing huge power loss reduction. For
example, a FET with 20mOhm R
60mV voltage drop at 3A; associated power
savings compared to the traditional diode ORing
(assuming typical 0.6V forward voltage drop) is
ten fold(0.18W vs. 1.8W)!
FET R
would be reduced by additional 90mW, which is
negligible compared to the power loss reduction
already achieved with 20mOhm FET. But to get
this negligible saving, the cost of the Active
ORing FET would increase significantly.
of the FET. The conduction loss could be
DS(on)
demonstrating
with
was 10mOhm. The power loss
IR5001S & (PbF)
traditional
performance
DS(on)
Now assume that
DS(on)
ORing
DS(on)
. To keep the
DS(on)
DS(on)
results in
DS(on)
, Active
DS(on)
of
of the
DS(on)
while
10
the
will
of
is