ISL62871HRUZ-T Intersil, ISL62871HRUZ-T Datasheet - Page 15

• Manufacturer Part Number: ISL62871HRUZ-T
• Description: IC CTRLR DC/DC PWM 16-TQFN
• Manufacturer: Intersil

Specifications of ISL62871HRUZ-T

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 16-UTQFN (16-µTQFN)
• Frequency-max: 330kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

means if the FB pin voltage falls below 102% x 1.0V = 1.02V
for more than 2µs, the LGATE gate-driver will turn off the
low-side MOSFET. If the output voltage rises again, the
LGATE driver will again turn on the low-side MOSFET when
the FB pin voltage is above the rising overvoltage threshold
V
load when there is a consistent overvoltage condition.
Undervoltage
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold V
than 2µs. For example if the converter is programmed to
regulate 1.0V at the FB pin, that voltage would have to fall
below the typical V
in order to trip the UVP fault latch. In numerical terms, that
would be 84% x 1.0V = 0.84V. When a UVP fault is declared,
the PGOOD pin will pull-down to 95Ω and latch-off the
converter. The fault will remain latched until the EN pin has
been pulled below the falling EN threshold voltage V
or if VCC has decayed below the falling POR threshold
voltage V
Over-Temperature
When the temperature of the IC increases above the rising
threshold temperature T
that suspends the PWM, forcing the LGATE and UGATE
gate-driver outputs low. The status of the PGOOD pin does
not change nor does the converter latch-off. The PWM
remains suspended until the IC temperature falls below the
hysteresis temperature T
operation resumes. The OTP state can be reset if the EN pin
is pulled below the falling EN threshold voltage V
VCC has decayed below the falling POR threshold voltage
V
while the IC is in the OTP state. It is likely that the IC will
detect an UVP fault because in the absence of PWM, the
output voltage decays below the undervoltage threshold
V
Theory of Operation
The modulator features Intersil’s R
Regulator technology, a hybrid of fixed frequency PWM
control and variable frequency hysteretic control. The PWM
frequency is maintained at 300KHz under static
continuous-conduction-mode operation within the entire
specified envelope of input voltage, output voltage, and
output load. If the application should experience a rising load
transient and/or a falling line transient such that the output
voltage starts to fall, the modulator will extend the on-time
and/or reduce the off-time of the PWM pulse in progress.
Conversely, if the application should experience a falling
load transient and/or a rising line transient such that the
output voltage starts to rise, the modulator will truncate the
on-time and/or extend the off-time of the PWM pulse in
progress. The period and duty cycle of the ensuing PWM
pulses are optimized by the R
VCC_THF
OVRTH
UVTH
.
for more than 2µs. By doing so, the IC protects the
VCC_THF
. All other protection circuits remain functional
.
UVTH
OTRTH
threshold of 84% for more than 2µs
OTHYS
15
3
, it will enter the OTP state
modulator for the remainder
at which time normal PWM
3
Robust-Ripple-
UVTH
ENTHF
ISL62871, ISL62872
for more
ENTHF
or if
of the transient and work in concert with the error amplifier
V
transient has dissipated and the control loop has recovered,
the PWM frequency returns to the nominal static 300KHz.
Modulator
The R
analog representation of the output inductor ripple current.
The duty-cycle of V
current through a ripple capacitor C
C
measures the input voltage (V
output voltage (V
V
V
The negative slope of V
Where, g
A window voltage V
amplifier output voltage V
which the ripple voltage V
V
V
is the lower threshold voltage and V
voltage. Figure 11 shows PWM pulses being generated as
V
switching frequency is proportional to the slew rates of the
positive and negative slopes of V
proportional to the voltage between V
Synchronous Rectification
A standard DC/DC buck regulator uses a free-wheeling
diode to maintain uninterrupted current conduction through
the output inductor when the high-side MOSFET switches off
for the balance of the PWM switching cycle. Low conversion
efficiency as a result of the conduction loss of the diode
V
ERR
R
RPOS
W
W
R
R
RNEG
FIGURE 11. MODULATOR WAVEFORMS DURING LOAD
RIPPLE CAPACITOR VOLTAGE C
can be written as Equation 27:
traverses the V
is provided by a transconductance amplifier g
is controlled internally by the IC. The V
signals feed into a window comparator in which V
3
to maintain output voltage regulation. Once the
modulator synthesizes an AC signal V
=
=
m
(
g
g
m
is the gain of the transconductance amplifier.
m
⋅
)
TRANSIENT
V
⋅
(
OUT
V
OUT
IN
W
R
W
–
⁄
C
) at the VO pin. The positive slope of
is the result of charge and discharge
and V
V
is referenced with respect to the error
R
OUT
ERROR AMPLIFIER VOLTAGE V
R
COMP
R
can be written as Equation
COMP
) C
is compared. The amplitude of
⁄
R
IN
R
, creating an envelope into
) at the PHASE pin and
R;
thresholds. The PWM
W
R
it is inversely
. The current through
W
WINDOW VOLTAGE V
is the higher threshold
and V
PWM
R,
V
COMP.
R
COMP,
, which is an
August 14, 2008
m
COMP
that
(EQ. 28)
(EQ. 27)
28:
COMP
FN6707.0
and
W