HIP6004DCR Intersil, HIP6004DCR Datasheet - Page 11

• Manufacturer Part Number: HIP6004DCR
• Description: IC CTRLR PWM VOLTAGE MON 20-QFN
• Manufacturer: Intersil

Specifications of HIP6004DCR

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1MHz
• Duty Cycle: 100%
• Voltage - Supply: 5 V ~ 12 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-TQFN Exposed Pad
• Frequency-max: 1MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

voltage-current transitions and do not adequately model power
loss due the reverse-recovery of the lower MOSFET’s body
diode. The gate-charge losses are dissipated by the HIP6004D
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Standard-gate MOSFETs are normally recommended for
use with the HIP6004D. However, logic-level gate MOSFETs
can be used under special circumstances. The input voltage,
upper gate drive level, and the MOSFET’s absolute gate-to-
source voltage rating determine whether logic-level
MOSFETs are appropriate.
Figure 9 shows the upper gate drive (BOOT pin) supplied by a
bootstrap circuit from V
develops a floating supply voltage referenced to the PHASE
pin. This supply is refreshed each cycle to a voltage of V
less the boot diode drop (V
turns on. Logic-level MOSFETs can only be used if the
MOSFET’s absolute gate-to-source voltage rating exceeds
the maximum voltage applied to VCC.
P
Where: D is the duty cycle = V
P
LOWER
UPPER
+
-
FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION
HIP6004D
+12V
V
t
F
SW
CC
= Io
S
= Io
is the switching frequency.
is the switch ON time, and
2
2
x r
x r
DS(ON)
DS(ON)
+ V
GND
D
BOOT
BOOT
UGATE
PHASE
LGATE
PGND
D
-
CC
x D +
x (1 - D)
. The boot capacitor, C
D
OUT
C
) when the lower MOSFET, Q
1
2
BOOT
11
SW
Io x V
/ V
IN
Q1
Q2
which increases the upper
+5V OR +12V
,
IN
x t
SW
D2
NOTE:
V
x F
NOTE:
V
G-S
G-S
S
BOOT
≈
≈
V
V
CC
CC
CC
-V
2
D
HIP6004D
Figure 10 shows the upper gate drive supplied by a direct
connection to V
converter systems where the main input voltage is +5V
less. The peak upper gate-to-source voltage is approximately
V
for the bias, the gate-to-source voltage of Q
level MOSFET is a good choice for Q
MOSFET can be used for Q
voltage rating exceeds the maximum voltage applied to V
FIGURE 10. UPPER GATE DRIVE - DIRECT V
Schottky Selection
Rectifier D
swing during the dead time between turning off the lower
MOSFET and turning on the upper MOSFET. The diode
must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is acceptable to
omit the diode and let the body diode of the lower MOSFET
clamp the negative inductor swing, but efficiency will drop
one or two percent as a result. The diode’s rated reverse
breakdown voltage must be greater than the maximum
input voltage.
CC
HIP6004D
-
+
less the input supply. For +5V main power and +12V
+12V
2
V
is a clamp that catches the negative inductor
CC
CC
GND
. This option should only be used in
BOOT
UGATE
PHASE
LGATE
PGND
2
if its absolute gate-to-source
Q
Q
+5V OR LESS
1
2
1
and a logic-level
D
1
CC
2
is 7V. A logic-
NOTE:
V
NOTE:
V
G-S
DRIVE OPTION
G-S
≈
≈
V
July 13, 2005
V
CC
CC
FN4855.3
DC
-5V
CC
DC
or
.