SC2596SETRT Semtech, SC2596SETRT Datasheet - Page 11

IC INTEGRTD DDR TERM REG 8-SOIC

SC2596SETRT

Manufacturer Part Number
SC2596SETRT
Description
IC INTEGRTD DDR TERM REG 8-SOIC
Manufacturer
Semtech
Datasheet

Specifications of SC2596SETRT

Applications
Converter, DDR
Number Of Outputs
1
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
8-SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Voltage - Input
-
Other names
SC2596SETR

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72
Application_5: Bode Plot of an all ceramic capacitor solution in Figure 5.
The phase margin is 72° and the bandwidth is around 1MHz, where: AVCC=3.3V, PVCC=VDDQ=1.8V, VTT=0.9V,
IOUT=380mA, COUT=10uF & 100mhom. For this application, we further measured the corresponding phase
margins for different output capacitor values and ESR values at designed sourcing and sinking currents in
Figure 7.
Layout guidelines
1) The SOIC8-EDP package of SC2596 can improve the thermal impedance (
pad should be add when PCB layout. Some thermal vias are required to connect the thermal pad to the PCB
ground layer. This will improve the thermal performance. Please refer to the recommanded landing pattern.
2) To increase the noise immunity, a ceramic capacitor of 100nF is required to decouple the V
shortest connection trace.
3) To reduce the noise on input power rail for standard SSTL-2 application, a 100
ceramic capacitor capacitor have to be used on the input power rail with shortest possible connection.
4) VTT output copper plane should be as large as possible. A 4.7uF to 10
decouple the VTT pin.
5) The trace between VSENSE pin and VTT rail should be as short as possible and put a 10nF ~100nF capacitor
close this vsense pin.
© 2009 Semtech Corp.
POWER MANAGEMENT
Application Information (Cont.)
90.00
80.00
70.00
60.00
50.00
40.00
30.00
20.00
10.00
0.00
10mR
Figure 7: Phase margin vs external ESR values for different output ceramic capacitor values
50mR
IO=380mA_Soure
Figure 6: Bode Plot of an all ceramic capacitor application
100mR
200mohm
Phase Margin vs External ESR
Cout=4.7uF
Cout=10uF
Cout=22uF
11
120.00
100.00
-20.00
-40.00
80.00
60.00
40.00
20.00
0.00
10mR
θ
50mR
JC
µ
) significantly. A suitable thermal
F capacitor have to be used to
IO=380mA_SINK
µ
F low ESR capacitor and a 1
100mR
200mohm
REF
www.semtech.com
SC2596
pin with the
Cout=4.7uF
Cout=10uF
Cout=22uF
µ
F

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