KSZ8993M Micrel Inc, KSZ8993M Datasheet - Page 39

• Manufacturer Part Number: KSZ8993M
• Description: IC SWITCH 10/100 3PORT 128PQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8993M

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII/SNI
• Power Supply Type: Analog/Digital
• Package Type: PQFP
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 1.89/3.465V
• Operating Supply Voltage (min): 1.71/3.135V
• Power Dissipation: 800mW
• Supply Current: 0.1/0.19A
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-1037

Rate Limiting Support
The KSZ8993M supports hardware rate limiting independently on the “receive side” and on the “transmit side” on
a per port basis. Rate limiting is supported in both priority and non-priority environment. The rate limit starts from
0 kbps and goes up to the line rate in steps of 32 kbps. The KSZ8993M uses “one second” as the rate limiting
interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to
count the number of bytes during the interval.
On the “receive side”, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets
on the port until the “one second” interval expires. Flow control can be enabled to prevent packet loss. If the rate
limit is programmed greater than or equal to 128 kbps and the byte counter is 8 Kbytes below the limit, flow
control will be triggered. If the rate limit is programmed lower than 128 kbps and the byte counter is 2 Kbytes
below the limit, flow control will also be triggered.
On the “transmit side”, if the number of bytes exceeds the programmed limit, the switch will stop transmitting
packets on the port until the “one second” interval expires.
If priority is enabled, the KSZ8993M can be programmed to support different rate limits for high priority packets
and low priority packets.
Configuration Interface
The KSZ8993M can operate as both a managed switch and an unmanaged switch.
In unmanaged mode, the KSZ8993M is typically programmed using an EEPROM. If no EEPROM is present, the
KSZ8993M is configured using its default register settings. Some defaults settings are configured via strap-in pin
options. The strap-in pins are indicated in the “KSZ8993M Pin Description and I/O Assignment” table.
I
With an additional I
“broadcast storm protection” and “rate control” without the need of an external processor.
For KSZ8993M I
(as defined in the KSZ8993M register map) with the exception of the “Read Only” status registers. After the de-
assertion of reset, the KSZ8993M will sequentially read in the configuration data for all 110 registers, starting from
register 0. The configuration access time (t
The following is a sample procedure for programming the KSZ8993M with a pre-configured EEPROM:
1. Connect the KSZ8993M to the EEPROM by joining the SCL and SDA signals of the respective devices. For
2
Micrel, Inc.
October 2008
C Master Serial Bus Configuration
the KSZ8993M, SCL is pin 97 and SDA is pin 98.
RST_N
SCL
SDA
2
C Master configuration, the EEPROM stores the configuration data for register 0 to register 109
2
C (“2-wire”) EEPROM, the KSZ8993M can perform more advanced switch features like
Figure 7. KSZ8993M EEPROM Configuration Timing Diagram
prgm
) is less than 15 ms, as depicted in the following figure.
39
t
prgm
....
....
....
<15 ms
M9999-020606
KSZ8993M/ML